Efficient network flow based min-cut balanced partitioning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 12, 1996, Pages 1533-1540

  Yang, Hannah Honghua ^a   Wong, D F ^b  

^a INTEL CORPORATION   (United States)

^b University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; HEURISTIC METHODS; MATHEMATICAL MODELS; NETWORKS (CIRCUITS); OPTIMIZATION; PROBLEM SOLVING; SIMULATED ANNEALING;

BALANCED BIPARTITION HEURISTIC; CIRCUIT PARTITIONING; COMBINATORIAL OPTIMIZATION TECHNIQUE; FLOW NETWORK;

INTEGRATED CIRCUIT LAYOUT;

EID: 0030378254     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.552086     Document Type: Article

References (27)

1. R. K. Brayton, R. Rudell, and A. L. Sangiovanni-Vincentelli, "MIS: A multiple-level logic optimization," IEEE Trans. Computer-Aided Design, pp. 1061-1081, Nov. 1987.
2. J. Cong and Y. Ding, "An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," in Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1992, pp. 48-53.
3. C.-K. Cheng, "Linear placement algorithms and applications to VLSI design," Networks, vol. 17, pp. 439-464, 1987.
4. J. Cong, L. Hagen, and A. Kahng, "Net partitions yield better module partitions," in Proc. 29th ACM/IEEE Design Automation Conf., 1992, pp. 47-52.
5. A. Dasdan and C. Aykanat, "Improved multiple-way circuit partitioning algorithms," in Int. ACM/SIGDA Wkshp. Field Programmable Gate Arrays, Feb. 1994.
6. W. E. Donath, "Logic partitioning," in Physical Design Automation of VLSI Systems, Preas and Lorenzetti, Eds. Menlo Park, CA: Benjamin/Cummins, 1988, pp. 65-86.
7. S. Even, Graph Algorithms. Potomac, MD: Computer Science Press, 1979.
8. J. R. Ford and D. R. Fulkerson, Flows in Networks. Princeton, NJ: Princeton Univ. Press, 1962.
9. C. M. Fiduccia and R. M. Mattheyses, "A linear time heuristic for improving network partitions," in Proc. ACM/IEEE Design Automation Conf., 1982, pp. 175-181.
10. R. Gomory and T. C. Hu, "Multi-terminal network flows," J. SIAM, vol. 9, pp. 551-570, 1961.
11. M. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. San Fransisco, CA: W. H. Freeman, 1979.
12. A. W. Goldberg and R. E. Tarjan, "A new approach to the maximum flow problem," J. SIAM, vol. 35, pp. 921-940, 1988.
13. J. Hwang and A. El Gamal, "Optimal replication for min-cut partition-ing," in Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1992, pp. 432-435.
14. J. Hwang and A. El Gamal, "Min-Cut replication in partitioned networks," IEEE Trans. Computer-Aided Design, vol. 14, pp. 96-106, Jan. 1995.
15. L. Hagen and A. B. Kahng, "Fast spectral methods for ratio cut partitioning and clustering," in Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1991, pp. 10-13.
16. T. C. Hu and K. Moerder, "Multiterminal flows in a hypergraph," in VLSI Circuit Layout: Theory and Design, Hu and Kuh, Eds. New York: IEEE Press, 1985, pp. 87-93.
17. S. Iman, M. Pedram, C. Fabian, and J. Cong, "Finding uni-directional cuts based on physical partitioning and logic restructuring," in 4th ACM/SIGDA Physical Design Wkshp., Apr. 1993.
18. E. Ihler, D. Wagner, and F. Wager, "Modeling hypergraphs by graphs with the same min-cut properties," in Info. Proc. Lett., vol. 45, pp. 171-175, 1993.
19. S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by simulated annealing," Sci., pp. 671-680, May 1983.
20. B. Kernighan and S. Lin, "An efficient heuristic procedure for partitioning of electrical circuits," Bell Syst. Tech. ]., pp. 291-307, Feb. 1970.
21. B. Krishnamurthy, "An improved min-cut algorithm for partitioning VLSI networks," IEEE Trans, on Computers, pp. 438-4446, May 1984.
22. E. Lawler, Combinatorial Optimization: Networks and Matroids. New York: Holt, Rinehart, and Winston, 1976.
23. B. M. Riess, K. Doll, and M. J. Frank, "Partitioning very large circuits using analytical placement techniques," in Proc. 31th ACM/IEEE Design Automation Conf., 1994, pp. 646-651.
24. L. A. Sanchis, "Multiway network partitioning," IEEE Trans. Comput., pp. 62-81, Jan. 1989.
25. Y. C. Wei and C. K. Cheng, "Toward efficient hierarchical designs by ratio cut partitioning," in Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1989, pp. 298-301.
26. H. Yang, "Algorithms for VLSI circuit partitioning," Ph.D. dissertation, The University of Texas at Austin, Aug. 1995.
27. H. Yang and D. F. Wong, "Edge-Map: Optimal performance driven technology mapping for iterative LUT based FPGA designs," in Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1994, pp. 150-155.