An Improved Min-Cut Algorithm For Partitioning VLSI Networks

IEEE Transactions on Computers

Volumn C-33, Issue 5, 1984, Pages 438-446

  Krishnamurthy, Balakrishnan ^a  

^a GE GLOBAL RESEARCH   (United States)

Author keywords

Partitioning algorithms; VLSI layout

Indexed keywords

COMPUTER PROGRAMMING - ALGORITHMS;

INTEGRATED CIRCUITS, VLSI;

EID: 0021425044     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1984.1676460     Document Type: Article

References (10)

1. A. V. Aho, J. E. Hopcroft, and J. D. Ullman, The Design and Analysis of Computer Algorithms. Reading, MA: Addison-Wesley, 1976.
2. S. B. Akers, “Clustering techniques for VLSI,’’ in Proc. IEEE Int. Symp. on Circuits and Systems, 1982, pp. 472–476.
3. M.A. Breuer, “Min-cut placement,” J. Design and Fault-Tolerant Computing, vol. I, no. 4, pp. 343–362, Oct. 1977.
4. “A class of min-cut placement algorithms,” in Proc. 14th Design Automation Conf., 1977, pp. 284–290.
5. L. I. Corrigan, “A placement capability based on partitioning,” in Proc. 16th Design Automation Conf., June 1979, pp. 406–413.
6. C. M. Fiduccia and R. M. Mattheyses, “A linear-time heuristic for improving network partitions,” in Proc. 19th Design Automation Conf., 1982, pp. 175–181.
7. M. R. Garey and D.S. Johnson, Computers and Intractability. San Fransisco, CA: Freeman, 1979, pp. 209–210.
8. B. W. Kemighan and S. Lin, “An efficient heuristic procedure for partitioning graphs,” Bell Syst. Tech. J., vol. 49, pp. 291–307, Feb. 1970.
9. D.G. Schweikert and B.W. Kemighan, “A proper model for the partitioning of electrical circuits,” in Proc. 9th Design Automation Work-shop, Dallas, TX, June 1979, pp. 57–62.
10. H. Shiraishi and F. Hirose, “Efficient placement and routing for master-slice LSI,” in Proc. 17th Design Automation Conf., Minneapolis, MN, June 1980, pp. 458–464.