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Volumn 17, Issue 4, 1987, Pages 439-464

Linear placement algorithms and applications to VLSI design

(1) Cheng, Chung‐Kuan a

a UNIVERSITY OF CALIFORNIA (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84986958745 PISSN: 00283045 EISSN: 10970037 Source Type: Journal
DOI: 10.1002/net.3230170406 Document Type: Article

Times cited : (21)

References (16)

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2
- 0021455306
- Module placement based on resistive network optimization. IEEE Trans. Computer‐Aided Design
- (1984) , pp. 218-225
- Cheng, C.K.¹ Kuh, E.S.²

3
- 84986953879
- Placement Algorithms and Applications to VLSI Design, Memorandum No. UCB/ERL M84/40 16 May.,. Electronics Research Laboratory Univ. of California, Berkeley.
- (1984)
- Cheng, C.K.¹

4
- 84987023652
- Decomposition algorithms for linear placement and applications to VLSI design. IEEE Int. Symposium on Circuits and Systems
- (1985)
- Cheng, C.K.¹

5
- 84957946170
- Princeton University Press, Princeton, NJ
- (1962) Flows in Networks
- Ford, L.R.¹ Fulkerson, D.R.²

6
- 84986978201
- (1956) Canad. J. Math. , vol.8

7
- 0003603813
- W. H. Freeman and Co., San Francisco
- (1979) Computers and Intractability—A Guide to the Theory of NP‐Completeness
- Garey, M.R.¹ Johnson, D.S.²

8
- 84987015061
- Multi‐terminal network flows
- (1961) Journal of the Society for Industrial and Applied Mathematics , vol.9 , pp. 551-570
- Gomory, R.E.¹ Hu, T.C.²

9
- 84986986525
- Single‐machine job sequencing and treelike precedence ordering and linear delay penalties. SIAM J. Appl. Math.
- (1972) , pp. 189-202
- Horn, W.A.¹

10
- 0020633645
- Linear ordering and application to placement. Proc. 20th Design Automation Conference
- (1983) , pp. 457-464
- Kang, S.¹

11
- 84990479742
- An efficient procedure for partitioning graphs. Bell Syst. Tech. J. Feb.
- (1970) , pp. 291-307
- Kernighan, B.W.¹ Lin, S.²

12
- 77951587888
- Sequencing jobs to minimize total weighted completion time subject to precedence constraints
- (1978) Ann. Discrete Math. , vol.2 , pp. 75-90
- Lawler, E.L.¹

13
- 0018520764
- One‐dimensional logic gate assignment and interval graphs. IEEE Trans Circuits and Systems
- (1979) , pp. 675-683
- Ohtsuki, T.¹ Mori, H.M.² Kuh, E.S.³ Kashiwabara, T.⁴ Fujisawa, T.⁵

14
- 85025020336
- Clustering and linear placement. Proc. 9th Design Automation Workshop
- (1972) , pp. 50-56
- Schuler, D.M.¹ Ulrich, E.G.²

15
- 0016483826
- Decomposition algorithms for single‐machine sequencing with precedence relations and deferral costs
- (1975) Operations Res. , vol.23 , pp. 283-298
- Sidney, J.B.¹

16
- 0020943701
- Interval‐graph‐based circuit layout. IEEE Int. Conf. on Computer‐Aided Design.
- (1983) , pp. 84-85
- Wing, O.¹

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.