Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn , Issue , 1994, Pages 150-155

  Yang, Honghua ^a   Wong, D F ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CALCULATIONS; COMPUTER NETWORKS; CONFORMAL MAPPING; DELAY CIRCUITS; HEURISTIC METHODS; ITERATIVE METHODS; LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; TABLE LOOKUP;

BENCHMARK CIRCUITS; EDGE MAP; FIELD PROGRAMMABLE GATE ARRAY; FLOW MAP; INTERCONNECTION EDGE; ITERATIVE LOOKUP TABLE; K FEASIBLE NETWORK; LOGIC BLOCKS; MAPPING ALGORITHM; OPTIMAL DELAY;

LOGIC DESIGN;

EID: 0028698960     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)