Optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

IEEE/ACM International Conference on Computer-Aided Design

Volumn , Issue , 1992, Pages 48-53

  Cong, Jason ^a   Ding, Yuzheng ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; BOOLEAN ALGEBRA; BOUNDARY ELEMENT METHOD; COMPUTATIONAL COMPLEXITY; GRAPH THEORY; LOGIC DESIGN; LOGIC GATES; MINIMIZATION OF SWITCHING NETS; TABLE LOOKUP; TESTING;

BOOLEAN NETWORK; DIRECTED ACYCLIC GRAPH; MINIMUM HEIGHT K-FEASIBLE CUT; POLYNOMIAL TIME TECHNOLOGY MAPPING ALGORITHM FLOW MAP;

ALGORITHMS;

EID: 0027003876     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.1992.279398     Document Type: Conference Paper

References (22)