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Information Processing Letters

Volumn 45, Issue 4, 1993, Pages 171-175

Modeling hypergraphs by graphs with the same mincut properties

(3) Ihler, Edmund a Wagner, Dorothea b Wagner, Frank c

a ETH ZURICH (Switzerland)

b TECHNISCHE UNIVERSITÄT BERLIN (Germany)

c FREIE UNIVERSITÄT BERLIN (Germany)

Author keywords

algorithm design; Combinatorial problems; VLSI layout

Indexed keywords

EID: 0007071645 PISSN: 00200190 EISSN: None Source Type: Journal
DOI: 10.1016/0020-0190(93)90115-P Document Type: Article

Times cited : (71)

References (7)

1
- 0001259868
- An algorithm for partitioning the nodes of a graph
- (1982) SIAM Journal on Algebraic Discrete Methods , vol.3 , pp. 541-550
- Barnes¹

2
- 0021412333
- A framework for solving VLSI graph layout problems
- (1984) J. Comput. System Sci. , vol.28 , pp. 300-343
- Bhatt¹ Leighton²

3
- 0009734567
- Packing paths, circuits, and cuts — A survey
- B. Korte et al., Springer, Berlin
- (1990) Paths, Flows, and VLSI-Layout , pp. 47-100
- Frank¹

4
- 84914960082
- University of Waterloo
- (1990) A new approximation technique for hypergraph partitioning problems, Manuscript
- Hadley¹

5
- 0003828819
- Teubner, Stuttgart and Wiley, Chichester, UK
- (1990) Combinatorial Algorithms for Integrated Circuit Layout
- Lengauer¹

6
- 85025041244
- A proper model for the partitioning of electrical circuits
- (1972) Proc. Ninth ACM/IEEE Design Automation Workshop , pp. 57-62
- Schweikert¹ Kernighan²

7
- 0025484904
- A Gomory-Hu cut tree representation of a netlist partitioning problem
- (1990) IEEE Trans. Circuits and Systems , vol.37 , pp. 1133-1139
- Vannelli¹ Hadley²

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.