Design and Test Rules for CMOS Circuits to Facilitate IDDQ Testing of Bridging Faults

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 11, Issue 5, 1992, Pages 659-670

  Lee, Kuen Jong ^a   Breuer, Melvin A ^b  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC CIRCUITS, COMBINATORIAL; LOGIC CIRCUITS, SEQUENTIAL; SEMICONDUCTOR DEVICE MANUFACTURE - SILICON ON INSULATOR TECHNOLOGY;

BICMOS CIRCUITS; BRIDGING FAULTS; CIRCUIT PARTITIONING MODEL; CURRENT SUPPLY MONITORING; EXCLUSIVE OR GATE; IDDQ TESTING;

INTEGRATED CIRCUITS, CMOS;

EID: 0026869827     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.127626     Document Type: Article

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