Transistor sizing for low power CMOS circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 6, 1996, Pages 665-671

  Borah, Manjit ^a   Owens, Robert Michael ^a   Irwin, Mary Jane ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; OPTIMIZATION; SIZING (FINISHING OPERATION); TRANSISTORS;

ACTIVE AREA; POWER CONSUMPTION; STATIC CIRCUIT; TRANSISTOR SIZING;

CMOS INTEGRATED CIRCUITS;

EID: 0030165115     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.503935     Document Type: Article

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