Delay Analysis of Series-Connected MOSFET Circuits

IEEE Journal of Solid-State Circuits

Volumn 26, Issue 2, 1991, Pages 122-131

  Sakurai, Takayasu ^a   Newton, A Richard ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC CIRCUITS; MICROELECTRONICS; SEMICONDUCTOR DEVICES, MOS--MODELING;

CARRIER VELOCITY SATURATION; CMOS GATE DELAY; SERIES CONNECTED MOSFET CIRCUITS; SHORT CHANNEL MOS MODEL;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0026106011     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.68126     Document Type: Article

References (9)

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3. T. Sakurai and A. R. Newton, “A simple short-channel MOSFET model and its application to delay analysis of inverters and series-connected MOSFET's,” in Proc. ISCAS, May 1990, TUAM-3-7; see also “A simple MOSFET model for circuit analysis and its application to CMOS gate delay analysis series-connected MOSFET structure, ” Dept. EECS, Univ. of Calif., Berkeley, ERL memo. Mar. 1990.
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