FET Scaling in Domino CMOS Gates

IEEE Journal of Solid-State Circuits

Volumn 20, Issue 5, 1985, Pages 1067-1071

  Shoji, Masakazu ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; LOGIC DEVICES - GATES; SEMICONDUCTOR DEVICES, MOS;

CARRY LOOK-AHEAD CIRCUITS; DOMINO CMOS GATES; FET SCALING;

TRANSISTORS, FIELD EFFECT;

EID: 0022135064     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1985.1052438     Document Type: Article

References (11)

1. J. A. Cooper, J. A. Copeland, R. H. Krambeck, D. C. Stanzione, and L. C. Thomas, “CMOS microprocessor for telecommunications applications,” in ISSCC 77 Dig., Feb. 1977, pp. 138–139.
2. R. H. Krambeck, C. M. Lee, and H. F. Law, “High speed compact circuits with CMOS,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 614–619, June 1982.
3. D. E. Blahut, A. K. Goksel, R. H. Krambeck, H. F. S. Law, P. M. Lu, W. F. Miller, and H. C. So, “The architecture and implementation of a 32 bit microprocessor with minicomputer performance,” presented at COMPCON, San Francisco, CA, Feb. 1982.
4. M. Shoji, “Electrical design of BELLMAC-32A microprocessor,” in ICCC Dig., Sept. 1982, pp. 112–115.
5. —, “Apparatus for increasing the speed of a circuit having a string of IGFETS,” U.S. Patent 4 430 583, Feb. 7, 1984.
6. L. W. Nagel, “Spice 2: A computer program to simulate semiconductor circuits,” Univ. California, Berkeley, CA, Tech. Memo ERI-M520, May 1975.
7. L. C. Parrillo, L. K. Wang, R. D. Swenumson, R. L. Field, R. C. Melin, and R. A. Levy, in IEDM Tech. Dig., 1982, p. 706.
8. J. R. Brews, “Physics of the MOS transistor,” in Appl. Solid State Sci., SUPPL. 2, Silicon Integrated Circuits, PART A. New York: Academic Press, 1981.
9. A. D. Lopez and H. F. Law, “A dense gate-matrix layout style for MOS LSI,” in ISSCC 80 Dig., Feb. 1980, pp. 212–213.
10. H. F. S. Law and M. Shoji, ‘PLA design for the BELLMAC-32A microprocessor,” in ICCC Dig., Sept. 1982, pp. 161–164.
11. N. P. Goncalres and H. J. de Man, “NORA: A racefree dynamic CMOS technique for pipelined logic structures,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 261–268, June 1983.