An Algorithm for CMOS Timing and Area Optimization

IEEE Journal of Solid-State Circuits

Volumn 19, Issue 5, 1984, Pages 781-787

  Lee, Charles M ^a   Soukup, Hana ^b  

^a LUCENT TECHNOLOGIES   (United States)

^b NORTEL NETWORKS   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SOFTWARE; ELECTRONIC CIRCUITS, DELAY TYPE; LOGIC DESIGN - OPTIMIZATION; SEMICONDUCTOR DEVICES, MOS - MATHEMATICAL MODELS;

DELAY-TIME OPTIMIZATION; LOGIC CHAIN; SILICON AREA;

INTEGRATED CIRCUITS, DIGITAL;

EID: 0021506574     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1984.1052221     Document Type: Article

References (3)

1. H. C. Lin and L. W. Linholm, “Optimized output stage for MOS integrated circuits,” IEEE J. Solid-State Circuits, Apr. 1975.
2. A. Kanuma, “CMOS circuit optimization,” Solid-State Electronics, vol. 26, no. 1, pp. 47–58, 1983.
3. C. Mead and L. Conway, Introduction to VLSI Systems, pp. 12–15.