Optimization of High-Speed CMOS Logic Circuits with Analytical Models for Signal Delay, Chip Area, and Dynamic Power Dissipation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 9, Issue 3, 1990, Pages 236-247

  Hoppe, Bernhard ^a   Neuendorf, Gerd ^a   Schmitt Landsiedel, Doris ^a   Specks, Will ^b  

^a SIEMENS AG   (Germany)

^b RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, VLSI--COMPUTER AIDED DESIGN; LOGIC DEVICES--GATES; SEMICONDUCTOR DEVICES, MOS--DESIGN;

ANALYTICAL MODELS; CHIP AREA; CMOS LOGIC CIRCUITS; DYNAMIC POWER DISSIPATION; SIGNAL DELAY; VLSI DESIGN;

LOGIC CIRCUITS;

EID: 0025398805     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.46799     Document Type: Article

References (30)

1. R. K. Brayton, G. D. Hachtel, and A. L. Sangiovanni-Vincentelli, “A survey of optimization techniques for integrated-circuit design,” Proc. IEEE, vol. 69, pp. 1334–1362, Oct. 1981.
2. A. E. Ruehli, P. K. Wolff, and G. Goertzel, “Analytical power/timing optimization technique for digital systems,” in Proc. 14th Design Automation Conf, pp. 142–146, 1977.
3. L. A. Glasser and L. P. J. Hoyte, “Delay and power optimization in VLSI circuits,” in Proc. 21st Design Automation Conf., pp. 529–535, 1984.
4. C. M. Lee and H. Soukup, “An algorithm for CMOS timing and area optimization,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 781–787, Oct. 1984.
5. K. S. Hedlund, “Aesop: A tool for automated transistor sizing,” in Proc. 24th Design Automation Conf., pp. 114–120, 1987.
6. M. D. Matson, “Optimization of digital MOS VLSI circuits,” in Proc. 1985 Chapel Hill Conf. on VLSI, pp. 109–126, 1985.
7. —, “Macromodeling of digital MOS VLSI circuits,” in Proc. 22nd Design Automation Conf., pp. 144–151, 1985.
8. M. D. Matson and L. A. Glasser, “Macromodeling and optimization of digital MOS VLSI circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 659–678, Oct. 1986.
9. D. P. Marple and A. E. Gammal, “Optimal selection of transistor sizes in digital VLSI circuits,” in Advanced Research in VLSI Proc. 1987 Standard Conf., Stanford, CA, pp. 151–172, 1987.
10. D. P. Marple, “Performance optimization of digital VLSI circuits,” Ph.D. dissertation, Stanford Univ., Oct. 1986; Tech. Rep., CSL-TR-86–308, Stanford Univ., 1986.
11. J. Shyu, A. Sangiovanni-Vincentelli, J. P. Fishburn, and A. E. Dunlop, “Optimization-based transistor sizing,” IEEE J. Solid-State Circuits, vol. 23, pp. 400–409, Apr. 1988.
12. J. P. Fishburn and A. E. Dunlop, “TILOS: A posynomial programming approach to transistor sizing,” in Proc. 1985 IEEE Conf. Computer-Aided Design, pp. 326–328, 1985.
13. N. Jouppi, “Timing analysis for nMOS VLSI,” in Proc. 20th Design Automation Conf., pp. 411–418, 1983.
14. S. Trimberger, “Automated performance optimization of custom integrated circuits,” in Proc. Int. Symp. on Circuits and Systems, pp. 194–197, 1983.
15. M. R. Lightner and S. W. Director, “Multiple criterion optimization of electronic circuits,” IEEE Trans. Circuits Syst., vol. CAS-28, pp. 169–179, Mar. 1981.
16. V. Chankong and Y. Y. Haimes, Multiobjective Decision Making: Theory and Methodology, North-Holland Series in System Science and Engineering. New York: Elsevier Science, 1983, vol. 8.
17. B. Hoppe, “Circuit optimization: Gate level modeling and multiobjective programming,” Microprocessing and Microprogramming, vol. 25, pp. 171–176, 1988.
18. L. W. Nagel, “SPICE2: A computer program to simulate semiconductor circuits,” Memo ERL-M520, Univ. California, Berkeley, 1975.
19. J. Rubinstein, P. Penfield Jr., and M. A. Horowitz, “Signal delay in RC networks,” IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 202–211, July 1983.
20. M. Shoji, “FET Scaling in Domino CMOS Gates,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 1067–1071, Oct. 1985.
21. N. Hedenstierna and K. O. Jeppson, “CMOS circuit speed and buffer optimization,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 270–281, Mar. 1987.
22. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981.
23. J. K. Ousterhout, “A switch level timing verifier for digital MOS VLSI,” IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 336–349, July 1985.
24. M. Annaratone, Digital CMOS Circuit Design. Boston MA: Kluwer Academic, 1986.
25. N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective. Reading, MA: Addison-Wesley, 1985.
26. D. J. Wilde and C. S. Beightler, Foundations of Optimization. Englewood Cliffs, NJ: Prentice-Hall, 1967.
27. B. Hoppe, “Mathematical techniques for low cost optimization of digital MOS circuits,” to be published.
28. D. Schmitt-Landsiedcl, G. Neuendorf. B. Hoppe, and H. J. Mattausch, “Hierarchical architecture for fast CMOS SRAM’s.” in Proc. 1989 COMP EURO Conf., to be published.
29. C. A. Mead and L. Conway. Introduction to VLSI Systems. Reading. MA: Addison-Wesley. 1980. section 8.2.
30. B. Hoppe, O. Kiehl. V. Eisele. T. Huber, D. Schmitt-Landsiedel, and G. Neuendorf, “Posynomial delay models for optimization-based transistor sizing in digital CMOS VLSI circuits.” in Proc. 1989 European Conf. on Circuit Theory and Design ECCTD’89, to be published.