Multiway VLSI circuit partitioning based on dual net representation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 4, 1996, Pages 396-409

  Cong, Jason ^a   Labio, Wilburt Juan ^a   Shivakumar, Narayanan ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; GRAPH THEORY; MATHEMATICAL TRANSFORMATIONS; VLSI CIRCUITS;

CIRCUIT PARTITIONING; DUAL NET REPRESENTATION; HYBRID DUAL NETLIST; MODULE CONTENTION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0030124580     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.494703     Document Type: Article

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