Multi-way VLSI circuit partitioning based on dual net representation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn , Issue , 1994, Pages 56-62

  Cong, Jason ^a   Labio, Wilburt ^a   Shivakumar, Narayanan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; MINIMIZATION OF SWITCHING NETS;

BIPARTITIONING ALGORITHMS; K-WAY PARTITIONING PROBLEM; MODULE CONTENTION PROBLEM; PREFERENCE FUNCTION;

VLSI CIRCUITS;

EID: 0028695105     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (19)