New Spectral Methods for Ratio Cut Partitioning and Clustering

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 11, Issue 9, 1992, Pages 1074-1085

  Hagen, Lars ^a   Kahng, Andrew B ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT LAYOUT;

RATIO CUT PARTITIONING; SPECTRAL METHODS;

VLSI CIRCUITS;

EID: 0026925324     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.159993     Document Type: Article

References (35)

1. E. R. Barnes, “An algorithm for partitioning the nodes of a graph.” SIAM J. Alg. Disc. Meth., vol. 7, no. 2, pp. 541–550, Apr. 1982.
2. R. B. Boppana, “Eigenvalues and Graph Bisection: An Average-Case Analysis,” in Proc. IEEE Symp. Found. Computer Sci., 1987, pp. 280–285.
3. T. N. Bui, S. Chaudhuri, F. T. Leighton, and M. Sipser, “Graph Bisection Algorithms with Good Average Case Behavior,” Combinatorica, vol. 7, no. 2, pp. 171–191, Feb. 1987.
4. H. R. Charney and D. L. Plato, “Efficient partitioning of components,” in Proc. IEEE Design Automation Workshop, 1968, pp. 16-0-16-21.
5. C. K. Cheng and T. C. Hu, “Maximum concurrent flow and minimum ratio cut,” Tech. Rep. CS88-141, Univ. of California, San Diego, Dec. 1988.
6. D. Cvetkovic, M. Doob, I. Gutman, and A. Torgasev, Recent Results in the Theory of Graph Spectra. New York: North-Holland, 1988.
7. W. E. Donath, “Logic partitioning,” in Physical Design Automation of VLSI Systems, B. Preas and M. Lorenzetti, Eds. Menlo Park, CA: Benjamin/Cummings, 1988, pp. 65–86.
8. W. E. Donath and A. J. Hoffman, “Lower bounds for the partitioning of graphs,” IBM J. Res. Dev., pp. 420–425, 1973.
9. C. M. Fiduccia and R. M. Mattheyses, “A linear time heuristic for improving network partitions,” in Proc. ACM/IEEE Design Automation Conf., 1982, pp. 175–181.
10. L. R. Ford, Jr. and D. R. Fulkerson, Flows in Networks. Princeton, NJ: Princeton University Press, 1962.
11. J. Frankle and R. M. Karp, “Circuit placement and cost bounds by eigenvector decompostion,” in Proc. IEEE Int. Conf. on Computer-Aided Design, 1986, pp. 414–417.
12. J. Garbers, H. J. Promel, and A. Steger, “Finding clusters in VLSI circuits,” extended version of paper in Proc. IEEE Int. Conf. on Computer-Aided Design, 1990, pp. 520–523.
13. M. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. San Francisco, CA: Freeman, 1979.
14. G. Golub and C. Van Loan, Matrix Computations. Baltimore, MD: Johns Hopkins Univ. Press, 1983.
15. K. M. Hall, “An r-dimensional quadratic placement algorithm,” Manag. Sci., vol. 17, pp. 219–229, 1970.
16. A. B. Kahng, “Fast hypergraph partition,” in Proc. ACM/IEEE Design Automation Conf., 1989, pp. 762–766.
17. B. W. Kernighan and S. Lin, “An efficient heuristic procedure for partitioning of electrical circuits,” Bell Syst. Tech. J., Feb. 1970.
18. S. Kirkpatrick, C. D. Gelatt Jr., and M. P. Vecchi, “Optimization by simulated annealing,” Science, vol. 220, pp. 671–680, 1983.
19. B. Krishnamurthy, “An improved min-cut algorithm for partitioning VLSI networks,” IEEE Trans. Computers, vol. 33, pp. 438–446, May 1984.
20. T. Leighton and S. Rao, “An approximate max-flow min-cut theorem for uniform multicommodity flow problems with applications to approximation algorithms,” in Proc. IEEE Ann. Symp. Found. Computer Sci., 1988, pp. 422–431.
21. T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout. Chichester, U.K.: Wiley-Teubner, 1990.
22. L. T. Pillage and R. A. Rohrer, “A quadratic metric with a simple solution scheme for initial placement,” in Proc. ACM/IEEE Design Automation Conf., 1988, pp. 324–329.
23. A. Pothen, H. D. Simon, and K. P. Liou, “Partitioning sparse matrices with eigenvectors of graphs,” SIAM J. Matrix Anal. Appl., vol. 11, pp. 430–452, 1990.
24. L. A. Sanchis, “Multiple-way network partitioning,” IEEE Trans. Computers, vol. 38, pp. 62–81, 1989.
25. D. G. Schweikert and B. W. Kernighan, “A proper model for the partitioning of electrical circuits,” in Proc. ACM/IEEE Design Automation Conf., 1972, pp. 57–62.
26. C. Sechen, “Placement and global routing of integrated circuits using simulated annealing,” Ph.D. dissertation, Univ. of Calfornia, Berkeley, 1986.
27. R. S. Tsay and E. S. Kuh, “A unified approach to partitioning and placement,” Princeton Conf. Inf. and Comp., 1986.
28. G. Vijayan, “Partitioning logic on graph structures to minimize routing cost,” IEEE Trans. Computer-Aided Design, vol. 9, pp. 1326–1334, Dec. 1990.
29. Y. C. Wei and C. K. Cheng, “Towards efficient hierarchical designs by ratio cut partitioning,” in Proc. IEEE Int. Conf. on Computer-Aided Design, 1989, pp. 298–301.
30. Y. C. Wei and C. K. Cheng, “A two-level two-way partitioning algorithm,” in Proc. IEEE Int. Conf. on Computer-Aided Design, 1990, pp. 516–519.
31. Y. C. Wei, “Circuit partitioning and its applications to VLSI designs,” Ph.D. dissertation, Univ. of California, San Diego, Sept. 1990.
32. Y. C. Wei and C. K. Cheng, “Ratio cut partitioning for hierarchical designs,” IEEE Trans. Computer-Aided Design, vol. 10, pp. 911–921, July 1991.
33. C. W. Yeh, C. K. Cheng, and T. T. Lin, “A general purpose multiple way partitioning algorithm,” in Proc. ACM/IEEE Design Automation Conf., June 1991, pp. 421–426.
34. B. Mohar, “The Laplacian spectrum of graphs.” in Graph Theory, Combinatorics, and Applications, Y. Alavi et. al. Eds., New York: Wiley, 1988, pp. 871–898.
35. L. Hagen and A. B. Kahng, “Fast spectral methods for ratio cut partitioning and clustering,” in Proc. IEEE Int. Conf. Computer-Aided Design, Santa Clara, CA, 1991, pp. 10–13.