On Area/Depth Trade-Off in LUT-Based FPGA Technology Mapping

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 2, Issue 2, 1994, Pages 137-148

  Cong, Jason ^a   Ding, Yuzheng ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTER ARCHITECTURE; CONFORMAL MAPPING; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; POLYNOMIALS; TABLE LOOKUP; TECHNOLOGY; VLSI CIRCUITS;

AREA MINIMUM MAPPING SOLUTION; BOOLEAN NETWORK; DEPTH RELAXATION OPERATION; DEPTH TRADE OFF; FIELD PROGRAMMING GATE ARRAY;

LOGIC GATES;

EID: 0028455029     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.285741     Document Type: Article

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