Hierarchical bit-line architecture with flexible redundancy and block compare test for 256Mb DRAM

1993 Symposium on VLSI Circuits Digest of Technical Papers

Volumn , Issue , 1993, Pages 93-94

  Asakura, Mikio ^a   Oishi, Tsukasa ^a   Tomishima, Shigeki ^a   Hidaka, Hideto ^a   Arimoto, Kazutami ^a   Fujishima, Kazuyasu ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

MICROPROCESSOR CHIPS;

BIT-LINE RESISTANCE; BLOCK COMPARE TEST (BCT); FLEXIBLE REDUNDANT SCHEME; HIERARCHICAL BIT-LINE PARASITIC CAPACITANCE;

RANDOM ACCESS STORAGE;

EID: 0027840453     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)