SOI-DRAM circuit technologies for low power high speed multi-giga scale memories

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1995, Pages 103-104

  Kuge, S ^a   Tsuruda, T ^a   Tomishima, S ^a   Tsukude, M ^a   Yamagata, T ^a   Arimoto, K ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CIRCUIT THEORY; COMPUTER SIMULATION; ELECTRIC CURRENTS; ESTIMATION; LOGIC CIRCUITS; MOS DEVICES; RANDOM ACCESS STORAGE; REDUNDANCY; SEMICONDUCTOR JUNCTIONS; TRANSISTORS; VOLTAGE CONTROL;

BIT LINE ISOLATION; BODY BIAS CONTROLLING TECHNIQUE; COLUMN SELECT LINE; HIGH SPEED ACCESS; LOW POWER HIGH SPEED MULTI-GIGA SCALE MEMORIES; PERIPHERAL CIRCUITS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0029544885     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)