Fault-tolerant designs for 256Mb DRAM

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1995, Pages 107-108

  Kirihata, T ^a   Watanabe, Y ^a   Wong, H ^a   DeBrosse, J ^a   Yoshida, M ^a   Katoh, D ^a   Fujii, S ^a   Wordeman, M ^a   Poechmueller, P ^a   Parke, S ^a   Asao, Y ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; COMPUTER ARCHITECTURE; COMPUTER CIRCUITS; COMPUTER HARDWARE; DATA COMPRESSION; DATA TRANSFER; FAULT TOLERANT COMPUTER SYSTEMS; LIMITERS; MICROPROCESSOR CHIPS; MOS DEVICES; REDUNDANCY;

COLUMN REDUNDANCY; COLUMN SELECT LINES; CONVENTIONAL REDUNDANCY ARCHITECTURE;

RANDOM ACCESS STORAGE;

EID: 0029516764     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)