-
2
-
-
0015372855
-
-
1972.
-
D.H. Eaton and C.-T. Sah, "Frequency response of Si-SiO? interface states on thin oxide MOS capacitors," Phys. Slat. Sol. (a), vol. 12, pp. 95-109, 1972.
-
C.-T. Sah, "Frequency Response of Si-SiO? Interface States on Thin Oxide MOS Capacitors," Phys. Slat. Sol. (A), Vol. 12, Pp. 95-109
-
-
Eaton, D.H.1
-
4
-
-
0004032396
-
-
Singapore: World Scientific Publishing Co., 1991.
-
For background, see Section 683 on pp. 662-666 and Section 412 on pp. 347-354 in Chih-Tang Sah, Fundamentals ofSolid-State Electronics. Singapore: World Scientific Publishing Co., 1991.
-
Fundamentals OfSolid-State Electronics.
-
-
Sah, C.-T.1
-
5
-
-
33747015144
-
-
55-69.
-
J.R. Schrieffer, "Mobility in inversion layers: Theory and experiment," in Semiconductor Surface Physics, R. H. Kingston, Ed. Philadelphia: University of Pennsylvania Press, 1957, pp. 55-69.
-
"Mobility in Inversion Layers: Theory and Experiment," in Semiconductor Surface Physics, R. H. Kingston, Ed. Philadelphia: University of Pennsylvania Press, 1957, Pp.
-
-
Schrieffer, J.R.1
-
6
-
-
0013456857
-
-
1955.
-
_ "Effective carrier mobility in surface-space charge layers," Physical Review, vol. 97, no. 3, pp. 641-648, Feb. 1955.
-
In Surface-space Charge Layers," Physical Review, Vol. 97, No. 3, Pp. 641-648, Feb.
-
-
Mobility, C.1
-
7
-
-
0018457253
-
-
1979.
-
T.H. King, P. W. Cook, R. H. Denard, C. M. Osburn, S. E. Schuster, and H. N. Yu, "l /im MOSFET VLSI technology: Part IV-Hot electron design constraints," IEEE Trans. Electron Devices, vol. 26, no. 4, pp. 346-352, Apr. 1979.
-
P. W. Cook, R. H. Denard, C. M. Osburn, S. E. Schuster, and H. N. Yu, "L /Im MOSFET VLSI Technology: Part IV-Hot Electron Design Constraints," IEEE Trans. Electron Devices, Vol. 26, No. 4, Pp. 346-352, Apr.
-
-
King, T.H.1
-
8
-
-
33746957207
-
-
153-162.
-
C.-T. Sah, "VLSI device reliability modeling," in Proc. Int. Symp. VLSI Technology. Systems and Applications, invited paper 5-1, Publisher: TSPC(C60), ERSO, ITRI, no. 195-4, Chung Hsing Rd. Sec. 4, Chu Tung, Hsinchu, Taiwan 31015, May 1987, pp. 153-162.
-
"VLSI Device Reliability Modeling," in Proc. Int. Symp. VLSI Technology. Systems and Applications, Invited Paper 5-1, Publisher: TSPC(C60), ERSO, ITRI, No. 195-4, Chung Hsing Rd. Sec. 4, Chu Tung, Hsinchu, Taiwan 31015, May 1987, Pp.
-
-
Sah, C.-T.1
-
10
-
-
0027606658
-
-
1993.
-
Y. Taur, S. Cohen, S. Wind, T. Lii, C. Hsu, D. Quinlan, C. A. Chang, D. Buchanan, P. Agneloo, Y. Mii, C. Reeves, A. Acovic, and V. Kesan, "Experimental O.lpm p-channel MOSFET with p+-polysilicon gate on 35 A gate oxide," IEEE Electron Device Lett., vol. 14, no. 6, pp. 304-306, June 1993.
-
S. Cohen, S. Wind, T. Lii, C. Hsu, D. Quinlan, C. A. Chang, D. Buchanan, P. Agneloo, Y. Mii, C. Reeves, A. Acovic, and V. Kesan, "Experimental O.lpm P-channel MOSFET with P+-polysilicon Gate on 35 A Gate Oxide," IEEE Electron Device Lett., Vol. 14, No. 6, Pp. 304-306, June
-
-
Taur, Y.1
-
11
-
-
0027879328
-
-
1993.
-
Y. Taur, S. Wind, Y. J. Mil, Y. Lu, D. Moy, K. A. Jenkins, C. L. Chen, P. J. Coane, D. Klaus, J. Bucchignano, M. Rosenfeld, M. G. R. Thompson, and M. Polcari, "High performance 0.1 //m CMOS devices with 1.5 V power supply," IEDM Tech. Dig., pp. 127-130, Dec. 1993.
-
S. Wind, Y. J. Mil, Y. Lu, D. Moy, K. A. Jenkins, C. L. Chen, P. J. Coane, D. Klaus, J. Bucchignano, M. Rosenfeld, M. G. R. Thompson, and M. Polcari, "High Performance 0.1 //M CMOS Devices with 1.5 V Power Supply," IEDM Tech. Dig., Pp. 127-130, Dec.
-
-
Taur, Y.1
-
12
-
-
0027680704
-
-
1993.
-
G.G. Shahidi, J. Warnock, S. Fischer, P. A. McFarland, A. Acovic, S. Subbanna, E. Ganin, E. Crabbe, J. Comfort, J. Y.-C. Sun, T. H. Ning, and B. Davari, "High performance devices for a 0.15 -4m CMOS technology," IEEE Electron Devices Leu., vol. 14, no. 10, pp. 466-4168, Oct. 1993.
-
J. Warnock, S. Fischer, P. A. McFarland, A. Acovic, S. Subbanna, E. Ganin, E. Crabbe, J. Comfort, J. Y.-C. Sun, T. H. Ning, and B. Davari, "High Performance Devices for A 0.15 -4m CMOS Technology," IEEE Electron Devices Leu., Vol. 14, No. 10, Pp. 466-4168, Oct.
-
-
Shahidi, G.G.1
-
13
-
-
0028192803
-
-
1994.
-
Y. Mii, S. Rishton, Y. Taur, D. Kern, T. Lii, K. Lee, K. A. Jenkins, D. Quinlan, T. Brown, Jr., D. Danner, F. Sewell, and M. Polcari, "Experimental high performance sub-O.l/im channel nMOSFET's." IEEE Trans. Electron Devices, vol. 15, no. 1, pp. 29-30, Jan. 1994.
-
S. Rishton, Y. Taur, D. Kern, T. Lii, K. Lee, K. A. Jenkins, D. Quinlan, T. Brown, Jr., D. Danner, F. Sewell, and M. Polcari, "Experimental High Performance Sub-O.l/im Channel NMOSFET's." IEEE Trans. Electron Devices, Vol. 15, No. 1, Pp. 29-30, Jan.
-
-
Mii, Y.1
-
14
-
-
0027878002
-
-
1993.
-
M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai, "Sub-50 nm gate length N-MOSFETS with 10 nm phosphorus source and drain junctions," IEDM Tech. Dig., pp. 119-122, Dec. 1993.
-
M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai, "Sub-50 Nm Gate Length N-MOSFETS with 10 Nm Phosphorus Source and Drain Junctions," IEDM Tech. Dig., Pp. 119-122, Dec.
-
-
Ono, M.1
-
15
-
-
0027813429
-
-
1993.
-
T. Ohguro, K. Yamada, N. Sugiyama, K. Usuda, Y. Akasaka, T. Yoshitomi, C. Fiegna, M. Ono, M. Saito, and H. Iwai, "Tenth micron P-Mosfet's with ultra-thin epitaxial channel layer grown by ultra-highvacuum CVD," IEDM Tech. Dig., pp. 433-436, Dec. 1993.
-
K. Yamada, N. Sugiyama, K. Usuda, Y. Akasaka, T. Yoshitomi, C. Fiegna, M. Ono, M. Saito, and H. Iwai, "Tenth Micron P-Mosfet's with Ultra-thin Epitaxial Channel Layer Grown by Ultra-highvacuum CVD," IEDM Tech. Dig., Pp. 433-436, Dec.
-
-
Ohguro, T.1
-
16
-
-
0005469038
-
-
1993.
-
M. Iwase, T. Mizuno, M. Takahashi, H. Niiyama, M. Fukumoto, K. Ishida, S. Inaba, Y. Takigami, A. Sanda, A. Toriumi, and M. Yoshimi, "High-performance 0.10-5 m CMOS devices operating at room temperature." IEEE Trans. Electron Devices, vol. 14, no. 2, pp. 51-53, Feb. 1993.
-
T. Mizuno, M. Takahashi, H. Niiyama, M. Fukumoto, K. Ishida, S. Inaba, Y. Takigami, A. Sanda, A. Toriumi, and M. Yoshimi, "High-performance 0.10-5 M CMOS Devices Operating at Room Temperature." IEEE Trans. Electron Devices, Vol. 14, No. 2, Pp. 51-53, Feb.
-
-
Iwase, M.1
-
17
-
-
0027845137
-
-
1993.
-
K.F. Lee, R. H. Yan, D. Y. Jeon, G. M. Chin, Y. O. Kim, D. M. Tennant, B. Razavi, H. D. Lin, Y. G. Wey, E. H. Westerwick, M. D. Morris, R. W. Johnson, T. M. Liu, M. Tarsia, M. Cerullo, R. G. Swartz, and A. Ourmazd, "Room temperature O.I /im CMOS technology with 11.8 ps gate delay," IEDM. Tech. Dig., pp. 131-134, Dec. 1993.
-
R. H. Yan, D. Y. Jeon, G. M. Chin, Y. O. Kim, D. M. Tennant, B. Razavi, H. D. Lin, Y. G. Wey, E. H. Westerwick, M. D. Morris, R. W. Johnson, T. M. Liu, M. Tarsia, M. Cerullo, R. G. Swartz, and A. Ourmazd, "Room Temperature O.I /Im CMOS Technology with 11.8 Ps Gate Delay," IEDM. Tech. Dig., Pp. 131-134, Dec.
-
-
Lee, K.F.1
-
18
-
-
0029379026
-
-
1994.
-
A. Neugroschel, C.-T. Sah, K. M. Han, M. S. Carroll, T. Nishida, J. T. Kavalieros, and Y. Lu, "Direct-current measurements of oxide and interface traps on oxidized silicon," IEEE Tram. Electron Devices, vol. 42, no. 9, pp. 1657-1662, Sept. 1, 1994.
-
C.-T. Sah, K. M. Han, M. S. Carroll, T. Nishida, J. T. Kavalieros, and Y. Lu, "Direct-current Measurements of Oxide and Interface Traps on Oxidized Silicon," IEEE Tram. Electron Devices, Vol. 42, No. 9, Pp. 1657-1662, Sept. 1
-
-
Neugroschel, A.1
-
19
-
-
36549098150
-
-
1988.
-
C.H. Hsu, T. Nishida, and C.-T. Sah, "Observation of threshold oxide electric field for trap generation in oxide films on silicon," J. Appl. Phys., vol. 63, no. 12, pp. 5882-5884, Dec. 1988.
-
T. Nishida, and C.-T. Sah, "Observation of Threshold Oxide Electric Field for Trap Generation in Oxide Films on Silicon," J. Appl. Phys., Vol. 63, No. 12, Pp. 5882-5884, Dec.
-
-
Hsu, C.H.1
-
20
-
-
0001323947
-
-
1992.
-
2 by electron-impact emission of trapped electrons," / Appl. Phys., vol. 72, no. 10, pp. 4683-4695, Nov. 1992.
-
2 by Electron-impact Emission of Trapped Electrons," / Appl. Phys., Vol. 72, No. 10, Pp. 4683-4695, Nov.
-
-
Thompson, S.E.1
-
21
-
-
33746968962
-
-
422.
-
C.-T. Sah and T. Nishida, "Mechanisms of electronic trapping in SiOj on Si," Invited Plenary paper by C. T. Sah in Proc. 21st Int. Conf. Physics of Semiconductors Singapore: World Scientific, July 1992, vol. 1, pp. 28-39. See also C.-T. Sah, Fundamentals of Solid-State Eleclmics-Study Guide. Singapore: World Scientific, 1993, Fig. B3.3 on p. 421 and Fig. B3.4 on p. 422.
-
And T. Nishida, "Mechanisms of Electronic Trapping in SiOj on Si," Invited Plenary Paper by C. T. Sah in Proc. 21st Int. Conf. Physics of Semiconductors Singapore: World Scientific, July 1992, Vol. 1, Pp. 28-39. See Also C.-T. Sah, Fundamentals of Solid-State Eleclmics-Study Guide. Singapore: World Scientific, 1993, Fig. B3.3 on P. 421 and Fig. B3.4 on P.
-
-
Sah, C.-T.1
-
22
-
-
0011053201
-
-
1995.
-
Y. Lu and C.-T. Sah, "Thermal emission of trapped holes in SiOj films," J. Appl. Phys., vol. 78(5), pp. 3156-3157, Sept. 1, 1995.
-
And C.-T. Sah, "Thermal Emission of Trapped Holes in SiOj Films," J. Appl. Phys., Vol. 78(5), Pp. 3156-3157, Sept. 1
-
-
Lu, Y.1
-
23
-
-
0000243365
-
-
1994.
-
_ "Two pathways of positive oxide-charge buildup during electron tunneling into silicon dioxide film," J. Appl. Phys., vol. 76, no. 8, pp. 4724-4727, Oct. 15, 1994.
-
Positive Oxide-charge Buildup during Electron Tunneling into Silicon Dioxide Film," J. Appl. Phys., Vol. 76, No. 8, Pp. 4724-4727, Oct. 15
-
-
Of, P.1
-
24
-
-
0019622395
-
-
1981.
-
S.K. Lai and D. R. Young, "Effects of avalanche injection of electrons into silicon dioxide-generation of fast and slow interface states," J. Appl. Phys., vol. 52, no. 10, pp. 6231-6240, Oct. 1981.
-
D. R. Young, "Effects of Avalanche Injection of Electrons into Silicon Dioxide-generation of Fast and Slow Interface States," J. Appl. Phys., Vol. 52, No. 10, Pp. 6231-6240, Oct.
-
-
Lai, S.K.1
-
25
-
-
0020751109
-
-
1983.
-
S.K. Lai. "Interface trap generation in silicon dioxide when electrons are captured by trapped holes," / Appl. Phys., vol. 54, no. 5, pp. 2540-2546, May 1983.
-
"Interface Trap Generation in Silicon Dioxide When Electrons Are Captured by Trapped Holes," / Appl. Phys., Vol. 54, No. 5, Pp. 2540-2546, May
-
-
Lai, S.K.1
-
26
-
-
33746946300
-
-
Lett.
-
C.-T. Sah, A. Neugroschel, K. M. Han, and J. T. Kavalieros, "Profiling interface trap density by the DC1V method," to be published in IEEE Electon Device Lett.
-
A. Neugroschel, K. M. Han, and J. T. Kavalieros, "Profiling Interface Trap Density by the DC1V Method," to Be Published in IEEE Electon Device
-
-
Sah, C.-T.1
|