-
1
-
-
0023548196
-
Experimental technology and characterization of self-aligned 0.1 µm-gate-length low-temperature operation NMOS devices
-
G. Sai-Halasz, M. Wordeman, D. Kern, E. Ganin, S. Rishton, H. Ng, D. Zicherman, D. Moy, T. Chang, and R. Dennard Experimental technology and characterization of self-aligned 0.1 µm-gate-length low-temperature operation NMOS devices, in IEDM Tech. Dig., 1987, p. 397.
-
(1987)
IEDM Tech. Dig.
, pp. 397.
-
-
Sai-Halasz, G.1
Wordeman, M.2
Kern, D.3
Ganin, E.4
Rishton, S.5
Ng, H.6
Zicherman, D.7
Moy, D.8
Chang, T.9
Dennard, R.10
-
2
-
-
0023120271
-
Submicrometer-channel CMOS for low-temperature operation
-
J. Sun, Y. Taur, R. Dennard, and S. Klepner, Submicrometer-channel CMOS for low-temperature operation, IEEE Trans. Electron Devices, vol. 34, p. 19, 1987.
-
(1987)
IEEE Trans. Electron Devices
, vol.34
, pp. 19
-
-
Sun, J.1
Taur, Y.2
Dennard, R.3
Klepner, S.4
-
3
-
-
0020242301
-
A half micron MOSFET using double implanted LDD
-
S. Ogura, C. Codella, N. Rovedo, J. Shepard, and J. Riseman, A half micron MOSFET using double implanted LDD, in IEDM Tech. Dig., 1982, p. 718.
-
(1982)
IEDM Tech. Dig
, pp. 718.
-
-
Ogura, S.1
Codella, C.2
Rovedo, N.3
Shepard, J.4
Riseman, J.5
-
4
-
-
84866212857
-
High transconductance 0.1 µ m pMOSFET
-
Y. Taur, S. Cohen, S. Wind T. Lii, C. Hsu, D. Quinlan, C. A. Chang, D. Buchanan, P. Agnello, Y. Mii, C. Reeves, A. Acovic, and V. Kesan.
-
(1992)
IEDM Tech. Dig.
, pp. 901.
-
-
Taur, Y.1
Cohen, S.2
Wind, S.3
Lii, T.4
Hsu, C.5
Quinlan, D.6
Chang, C.A.7
Buchanan, D.8
Agnello, P.9
Mii, Y.10
Reeves, C.11
Acovic, A.12
Kesan, V.13
-
5
-
-
85033822923
-
High performance 0.1m nMOSFET's with 10 ps/stage delay (85 K) at 1.5 V power supply
-
High transconductance 0.1 µ m pMOSFET, in IEDM Tech. Dig., 1992, p.901.
-
Tech. Dig. 1993 VLSI Symp. VLSI Technol.
, pp. 91.
-
-
Mii, Y.1
Rishton, S.2
Taur, Y.3
Lii, T.4
Lee, K.5
Jenkins, K.6
Quinlan, D.7
Brown, T.8
Danner, D.9
Sewell, F.10
Polcari, M.11
-
6
-
-
0022751618
-
Analysis of the gate-voltage-dependent series resistance on MOSFET's
-
Y. Mii, S. Rishton, Y. Taur, T. Lii, K. Lee, K. Jenkins, D. Quinlan, T. Brown Jr., D. Danner, F. Sewell, and M. Polcari, High performance 0.1 μ m nMOSFET's with 10 ps/stage delay (85 K) at 1.5 V power supply, in Tech. Dig. 1993 VLSI Symp. VLSI Technol., p. 91.
-
(1986)
IEEE Trans. Electron Devices
, vol.33
, pp. 965
-
-
Ng, K.1
Lynch, W.2
-
7
-
-
0026869985
-
A new shift and ratio method for MOSFET channel-length extraction
-
K. Ng and W. Lynch. Analysis of the gate-voltage-dependent series resistance on MOSFET's, IEEE Trans. Electron Devices, vol. 33,p. 965, 1986.
-
(1992)
IEEE Electron Device Lett.
, vol.13
, pp. 267
-
-
Taur, Y.1
Zicherman, D.2
Lombardi, D.3
Restle, P.4
Hsu, C.5
Hanafi, H.6
Wordeman, M.7
Davari, B.8
Shahidi, G.9
-
8
-
-
0026869985
-
A new straightforward calibration and correction procedure for 'on wafer’ high frequency S-parameter measurements (45 MHz-I8 MHz)
-
Y. Taur, D. Zicherman, D. Lombardi, P. Restle, C. Hsu, H. Hanafi, M. Wordeman, B. Davari, and G. Shahidi, A new shift and ratio method for MOSFET channel-length extraction, IEEE Electron Device Lett., vol. 13, p. 267, 1992.
-
(1987)
IEEE BCTM Tech. Dig.
, pp. 70.
-
-
van, P.1
Wijnen, H.2
Claessen, H.3
Wolsheimer, E.4
-
9
-
-
33747667461
-
High performanceµm room temperature Si MOSFETs
-
P. van Wijnen, H. Claessen, and E. Wolsheimer, A new straightforward calibration and correction procedure for ‘on wafer’ high frequency S- parameter measurements (45 MHz-I8 MHz), in IEEE BCTM Tech. Dig., 1987, p. 70.
-
Tech. Dig. 1992 VLSI Symp. VLSI Technol
, pp. 86.
-
-
Yan, R.1
Lee, K.2
Jeon, D.3
Kim, Y.4
Park, B.5
Pinto, M.6
Rafferty, C.7
Tennant, D.8
Westerwick, E.9
Chin, G.10
Morris, M.11
Early, K.12
|