Direct-Current Measurements of Oxide and Interface Traps on Oxidized Silicon

IEEE Transactions on Electron Devices

Volumn 42, Issue 9, 1995, Pages 1657-1662

  Neugroschel, Arnost ^a   Sah, Chih Tang ^a   Han, K Michael ^a   Carroll, Michael S ^a   Nishida, Toshikazu ^a   Kavalieros, Jack Theodore ^a   Lu, Yi ^b  

^a UNIVERSITY OF FLORIDA   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENT COLLECTORS; ELECTRIC CURRENT MEASUREMENT; ELECTRIC RESISTANCE; HETEROJUNCTION BIPOLAR TRANSISTORS; INTERFACES (MATERIALS); MOSFET DEVICES; OXIDES; SEMICONDUCTING SILICON; VOLTAGE MEASUREMENT;

BIPOLAR JUNCTION TRANSISTORS; CHARGE PUMPING; DIRECT CURRENT CURRENT-VOLTAGE MEASUREMENT;

ELECTRIC VARIABLES MEASUREMENT;

EID: 0029379026     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.405281     Document Type: Article

References (21)

1. C.-T, Sah, Fundamentals of Solid-State Electronics. River Edge, NJ and Singapore: World Scientific, Nov. 1991.
2. C.-T, Sah, Fundamentals of Solid-State Electronics—Study Guide. River Edge, NJ and Singapore: World Scientific, Dec. 1993.
3. A. Neugroschel, C.-T. Sah, and M. S. Carroll, “Current-acceleration for rapid time-to-failure determination of bipolar junction transistors under emitter-base reverse-bias stress,” IEEE Trans. Electron Devices, vol. 42, no. 7, pp. 1380–1383, July 1995. (For a complete account of the original models proposed by Sah and Neugroschel, see SRC publication C94320.)
4. K. M. Han and T. Nishida, “Sequential substrate and channel hot electron injection to separate oxide and interface traps in n-MOST,” Solid-State Electron., vol. 38, pp. 105–113, Jan. 1995; for a review of the BiMOS structure and measurement method, see T. Nishida, Solid-State Electron., vol. 35, no. 3, pp. 357–369, March 1992.
5. C.-T. Sah, “A new semiconductor tetrode-the surface-potential controlled transistor,” in Proc. of IRE, vol. 49, Nov. 1961, pp. 1623–1634.
6. C.-T. Sah, “Effect of surface recombination and channel on p-n junction and transistor characteristics,” IRE Trans. Electron Devices, vol. ED-9, no. 1, pp. 94–108, Jan. 1962.
7. J. F. Verwey, “On the mechanism of hFE degradation by emitter-base reverse current stress,” Microelectronics and Reliability, vol. 9, pp. 425–432, 1970.
8. J. F. Verwey, “On the emitter degradation by avalanche breakdown in planar transistors,” Solid-State Electron., vol. 14, pp. 775–782, Sept. 1971.
9. B. A. McDonald, “Avalanche degradation of hFE,” IEEE Trans. Electron Devices vol. ED-17, pp. 871–878, Oct. 1970.
10. H. H. Berger, “The injection model-A structure oriented model for merged transistor logic,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 218–227, Oct. 1972.
11. H. E. Wulms, “Base current of I2L transistors,” IEEE J. Solid-State Circuits, vol. SC-12, pp. 143–150, Apr. 1977.
12. M. W. Hillen and J. Holsbrink, “The base current recombining at the oxidized silicon surface,” Solid-State Electron., vol. 26, pp. 453–463, May 1983.
13. M. Y. Ghannam, R. P. Mertens, R. F. De Keersmaecker, and R. J. Van Overstraeten, “Electrical characterization of the boron-doped Si-SiO2 interface,” IEEE Trans. Electron Devices, vol. ED-32, pp. 1264–1271, July 1985.
14. S. E. Thompson and T. Nishida, “Positive charge generation in SiO2 by electron-impact emission of trapped electron,” J. Appl. Phys., vol. 72, pp. 4683–4695, Nov. 1992.
15. C.-T. Sah and T. Nishida, “Mechanisms of electronic trapping in SiO2 on Si,” The Physics of Semiconductors. Singapore: World Scientific, vol. 1, pp. 28–40; also presented as the Plenary Presentation, 21th Int. Conf. Physics of Semiconductors, Beijing, Aug. 10–14, 1992.
16. A. S. Grove and D. J. Fitzgerald, “Surface effects on p-n junctions: Characteristics of surface space-charge regions under non-equilibrium conditions,” Solid-State Electron., vol. 9, pp. 783–806, Aug. 1966.
17. J. Bardeen, “Surface states and rectification at a metal semiconductor contact,” Phys. Rev., vol. 71, pp. 717–727, May 15, 1947.
18. C. A. Mead and W. G. Spitzer, “Fermi-level position at metal-semiconductor interfaces,” Phys. Rev., vol. 134, no. A713, 1964.
19. T. P. Ma, private communication at the SRC Annual Project Review, April 13, 1994.
20. C.-T. Sah, Fundamentals of Solid-State Electronics. River Edge, NJ and Singapore: World Scientific, Nov. 1991, 683.11, p. 666.
21. D. R. Young, private communication to C.-T. Sah, 1975. See also D. R. Young, E. A. Irene, D. J. DiMaria, and R. F. DeKeersmaecker, J Appl. Phys., vol. 50, no. 6366, 1979.