Power constraint scheduling of tests

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1994, Pages 271-274

  Chou, Richard M ^a   Saluja, Kewal K ^a   Agrawal, Vishwani D ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; ENERGY DISSIPATION; GRAPH THEORY; MATHEMATICAL MODELS; OPTIMIZATION; SCHEDULING; VLSI CIRCUITS;

BIPARTICLE RESOURCE ALLOCATION GRAPH; CLIQUE; POWER CONSTRAINT; TEST COMPATIBILITY GRAPH; TEST LENGTH; TEST SCHEDULING; TEST SESSION; TIME COMPATIBLE TESTS;

INTEGRATED CIRCUIT TESTING;

EID: 0027961637     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)