Bare die test

Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92

Volumn , Issue , 1992, Pages 24-27

  Parker, R H ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MICROPROCESSOR CHIPS; PROBES;

BARE DIES; DEVELOPMENT COSTS; OVERLAY TECHNIQUES; THIN FILM MEMBRANE;

DIES;

EID: 85030111410     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MCMC.1992.201438     Document Type: Conference Paper

References (4)

1. Leslie, Brian and Matta, Farid "Wafer-Level Testing With a Membrand Probe" IEEE Design And Test of Computers, Vol. 89, pp. 10-15, 1989.
2. Leslie, Brian and Matta, Farid "Membrane Probe Card Technology (The Future for High Performance Wafer Test)" Proceedings of the IEEE 1988 International Test Conference.
3. C. W. Eichelberger, R. J. Wojnarowski et al "Wafer Scale Integration Technology Demonstration, (Final Report for Phase2A and Phase 2A Extension)" GE-CRD Document 89SRD007, pp. 99-106, Aug. 25, 1989.
4. J. Reagan, Julie Andrade, Gail Kieve "Thin Film Hybrid Technology for On-Wafer Probing of Integrated Circuits" Hybrid Circuit Technology, pp. 13-20, April 1990.