Technology Mapping for low power

Proceedings - Design Automation Conference

Volumn , Issue , 1993, Pages 74-79

  Tiwari, Vivek ^a   Ashar, Pranav ^a   Malik, Sharad ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC GATES; MAPPING; NUMERICAL ANALYSIS; TECHNOLOGY;

POWER DISSIPATION; TECHNOLOGY MAPPING;

CMOS INTEGRATED CIRCUITS;

EID: 0027228668     PISSN: 01467123     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)