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Volumn 38, Issue 1, 2004, Pages 43-67

Self-timed communication platform for implementing high-performance systems-on-chip

Author keywords

Architecture; Asynchronous; Bus; Platform; Ring; Self timed; SoC

Indexed keywords

ARCHITECTURE; BANDWIDTH; ELECTRIC CLOCKS; FREQUENCIES; LARGE SCALE SYSTEMS; OPTICAL INTERCONNECTS; THROUGHPUT; VLSI CIRCUITS;

EID: 9544258270     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2004.03.001     Document Type: Article
Times cited : (11)

References (21)
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  • 9
    • 0004093751 scopus 로고    scopus 로고
    • IBM Corporation, The CoreConnect Bus Architecture, specifications available at http://www.chips.ibm.com/products/coreconnect.
    • The CoreConnect Bus Architecture
  • 13
    • 0033890555 scopus 로고    scopus 로고
    • Bus architecture of a system on a chip with user- Configurable system logic
    • S. Winegarden, Bus architecture of a system on a chip with user- configurable system logic, IEEE J. Solid-State Circuits 35 (3) (2000) 425-433.
    • (2000) IEEE J. Solid-state Circuits , vol.35 , Issue.3 , pp. 425-433
    • Winegarden, S.1
  • 17
    • 84900861511 scopus 로고
    • Routing messages through networks: An exercise in deadlock avoidance
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    • (1987) Proceedings of OPPT
    • Roscoe, A.W.1
  • 19
    • 0001960299 scopus 로고
    • Asynchronous circuit design: Motivation, background and methods
    • G. Birtwistle, A. Davis (Eds.), Springer, Berlin
    • A. Davis, S.M. Nowick, Asynchronous circuit design: motivation, background and methods, in: G. Birtwistle, A. Davis (Eds.), Asynchronous Digital Circuit Design, Springer, Berlin, 1995, pp. 1-49.
    • (1995) Asynchronous Digital Circuit Design , pp. 1-49
    • Davis, A.1    Nowick, S.M.2
  • 21
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    • Power supply noise analysis methodology for deep-submicron VLSI chip design
    • Anaheim, CA
    • H.H. Chen, D.D. Ling, Power supply noise analysis methodology for deep-submicron VLSI chip design, in: Proceedings of Design Automation Conference (DAC), Anaheim, CA, 1997.
    • (1997) Proceedings of Design Automation Conference (DAC)
    • Chen, H.H.1    Ling, D.D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.