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Volumn 4, Issue , 2001, Pages 170-173

Asynchronous interface for locally clocked modules in ULSI systems

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS INTERFACE; BURST-MODE; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS; INTERFACE UNITS; MODULAR DESIGNS;

EID: 48649085363     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922199     Document Type: Conference Paper
Times cited : (6)

References (7)
  • 1
    • 0031353104 scopus 로고    scopus 로고
    • Asynchronous Wrapper for heterogeneous Systems
    • D. S. Bormann and P. Y. K. Cheung. Asynchronous Wrapper for heterogeneous Systems. In Proc. of the IEEEICCD'97, pp. 307-314,1997.
    • (1997) Proc. of the IEEEICCD'97 , pp. 307-314
    • Bormann, D.S.1    Cheung, P.Y.K.2
  • 2
    • 0001960299 scopus 로고
    • Asynchronous circuit design: Motivation, background and methods
    • In G. Birtwistle and A. Davis, editors. Springer
    • A. Davis and S.M. Nowick. Asynchronous circuit design: motivation, background and methods. In G. Birtwistle and A. Davis, editors, Asynchronous Digital Circuit Design, pages 1-49. Springer, 1995.
    • (1995) Asynchronous Digital Circuit Design , pp. 1-49
    • Davis, A.1    Nowick, S.M.2
  • 4
    • 77957961901 scopus 로고    scopus 로고
    • Practical design of globally-asynchronous locally-synchronous systems
    • April
    • J. Muttersbach, T. Villiger and W. Fichtner. Practical Design of Globally-Asynchronous Locally-Synchronous Systems. In Proc. of the IEEE ASYNC '2000, pp. 52-59, April 2000.
    • (2000) Proc. of the IEEE ASYNC '2000 , pp. 52-59
    • Muttersbach, J.1    Villiger, T.2    Fichtner, W.3
  • 5
    • 0032027374 scopus 로고    scopus 로고
    • Architectural optimization for low-power nonpipelined asynchronous systems
    • March
    • L. Plana and S. Nowick Architectural Optimization for Low-Power Nonpipelined Asynchronous Systems. In IEEE Trans, on VLSI Systems, 6(1) March 1998.
    • (1998) IEEE Trans, on VLSI Systems , vol.6 , Issue.1
    • Plana, L.1    Nowick, S.2
  • 6
    • 0001951703 scopus 로고
    • System timing
    • Chapter 7 in Mead and Conway, editors., Addison-Wesley
    • C. L. Seitz. System timing. Chapter 7 in Mead and Conway, editors. Introduction to VLSI Systems, Addison-Wesley, 1980.
    • (1980) Introduction to VLSI Systems
    • Seitz, C.L.1
  • 7
    • 0030403808 scopus 로고    scopus 로고
    • Pausible clocking: A first step towards heterogeneous systems
    • K. Y. Yun and R. P. Donohue Pausible Clocking: A First Step Towards Heterogeneous Systems. In roc. ofIEEElCCD'96, 1996.
    • (1996) Proc. of IEEElCCD'96
    • Yun, K.Y.1    Donohue, R.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.