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Volumn 35, Issue 3, 2000, Pages 425-433

Bus architecture of a system on a chip with user-configurable system logic

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC CIRCUITS; PIPELINE PROCESSING SYSTEMS; TABLE LOOKUP;

EID: 0033890555     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.826825     Document Type: Article
Times cited : (20)

References (8)
  • 2
    • 0032597714 scopus 로고    scopus 로고
    • An efficient bus architecture for system-on chip design
    • May
    • B. Cordan, "An efficient bus architecture for system-on chip design," in Proc. IEEE 1999 Custom Integrated Circuits Conf., May 1999, pp. 623-626.
    • (1999) Proc. IEEE 1999 Custom Integrated Circuits Conf. , pp. 623-626
    • Cordan, B.1
  • 4
    • 0343052785 scopus 로고    scopus 로고
    • May. [Online]
    • IBM blue logic on-chip bus overview (1999, May). [Online]. Available: http://www.chips.ibm.com/products/asics/products/cores/bus_over.html
    • (1999) IBM Blue Logic On-Chip Bus Overview
  • 5
    • 0032597875 scopus 로고    scopus 로고
    • A next generation architecture optimized for high density system level integration
    • May
    • R. Cliff, S. Reddy, and C. McClintock et al., "A next generation architecture optimized for high density system level integration," in Proc. IEEE 1999 Custom Integrated Circuits Conf., May 1999, pp. 175-178.
    • (1999) Proc. IEEE 1999 Custom Integrated Circuits Conf. , pp. 175-178
    • Cliff, R.1    Reddy, S.2    McClintock, C.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.