40-43-Gb/s OC-768 16:1 MUX/CMU Chipset with SFI-5 Compliance

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 12, 2003, Pages 2169-2180

  Tao, Hai ^a   Shaeffer, Derek K ^a   Xu, Min ^a   Benyamin, Saied ^a   Condito, Vincent ^a   Kudszus, Steffen ^a   Lee, Qinghung ^a   Ong, Adrian ^a   Shahani, Arvin ^a   Si, Xiaomin ^a   Wong, Wayne ^a   Tarsia, Maurice ^a  

^a Big Bear Networks   (United States)

Author keywords

Clock multiplying unit (CMU); Delay locked loop (DLL); Jitter generation; Multiplexer (MUX); OC 768; Optical networking; Optical transmission; Phase noise; Phase locked loop (PLL); SFI 5; SiGe; SONET

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEMULTIPLEXING; ELECTRON MOBILITY; ERROR CORRECTION; HETEROJUNCTIONS; JITTER; LIGHT TRANSMISSION; MODULATORS; MULTIPLEXING EQUIPMENT; OPTIMIZATION; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; POWER SUPPLY CIRCUITS; REGULATORY COMPLIANCE; SPECTRUM ANALYZERS;

CLOCK MULTIPLYING UNIT (CMU); DELAY-LOCKED LOOPS (DLL); JITTER GENERATION; OPTICAL NETWORKING;

INTEGRATED CIRCUITS;

EID: 9144256124     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.818575     Document Type: Conference Paper

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