Bounding DRAM interference in COTS heterogeneous MPSoCs for mixed criticality systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 37, Issue 11, 2018, Pages 2323-2336

  Hassan, Mohamed ^a,b   Pellizzoni, Rodolfo ^c  

^a Intel PSG   (Canada)

^b UNIVERSITY OF GUELPH   (Canada)

^c UNIVERSITY OF WATERLOO   (Canada)

Author keywords

DRAM; heterogeneous systems; memory; mixed criticality; multiple processors systems on chip (MPSoCs); real time systems; system on chip; timing analysis

Indexed keywords

CRITICALITY (NUCLEAR FISSION); DATA STORAGE EQUIPMENT; DYNAMIC RANDOM ACCESS STORAGE; INTERACTIVE COMPUTER SYSTEMS; MULTIPROCESSING SYSTEMS; SYSTEM-ON-CHIP;

COMMERCIAL OFF-THE SHELVES; CRITICAL APPLICATIONS; HETEROGENEOUS SYSTEMS; MIXED CRITICALITIES; MIXED-CRITICALITY SYSTEMS; SYNCHRONOUS DYNAMICS; SYSTEMS ON CHIPS; TIMING ANALYSIS;

REAL TIME SYSTEMS;

EID: 85055278844     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2018.2857379     Document Type: Article

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