Reverse-engineering embedded memory controllers through latency-based analysis

Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS

Volumn 2015-May, Issue , 2015, Pages 297-306

  Hassan, Mohamed ^a   Kaushik, Anirudh M ^a   Patel, Hiren ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; MAPPING; REVERSE ENGINEERING;

ADDRESS MAPPINGS; ANALYSIS TECHNIQUES; DRAM MEMORY; EMBEDDED MEMORY; MICRO ARCHITECTURES; MICRO-BENCHMARK;

MEMORY ARCHITECTURE;

EID: 84944685676     PISSN: 15453421     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTAS.2015.7108453     Document Type: Conference Paper

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