A composable worst case latency analysis for multi-rank DRAM devices under open row policy

Real-Time Systems

Volumn 52, Issue 6, 2016, Pages 761-807

  Wu, Zheng Pei ^a   Pellizzoni, Rodolfo ^a   Guo, Danlu ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

DRAM; Memory controller; Timing analysis

Indexed keywords

CONTROLLERS; EMBEDDED SYSTEMS; REAL TIME SYSTEMS;

BENCHMARK EVALUATION; COMMERCIAL OFF-THE SHELVES; GENERAL-PURPOSE SYSTEMS; MEMORY ACCESS LATENCY; MEMORY CONTROLLER; REAL TIME CONTROLLERS; REAL-TIME EMBEDDED SYSTEMS; TIMING ANALYSIS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84964043849     PISSN: 09226443     EISSN: 15731383     Source Type: Journal    
DOI: 10.1007/s11241-016-9253-4     Document Type: Article

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