Noise-aware DVFS transition sequence optimization for battery-powered IoT devices

Proceedings - Design Automation Conference

Volumn Part F137710, Issue , 2018, Pages

  Luo, Shaoheng ^a   Zhuo, Cheng ^a   Gan, Houle ^a  

^a ZHEJIANG UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; COMPUTER AIDED DESIGN; ELECTRIC BATTERIES; ELECTRIC POWER TRANSMISSION; NOISE ABATEMENT; SYSTEM-ON-CHIP;

BATTERY LIFETIME; INTERNET OF THINGS (IOT); LIMITED ENERGIES; LOW-POWER SYSTEMS; POWER DELIVERY NETWORK (PDN); SEQUENCE OPTIMIZATION; TRADITIONAL APPROACHES; TRANSITION SEQUENCES;

INTERNET OF THINGS;

EID: 85053698074     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/3195970.3196080     Document Type: Conference Paper

References (26)

1. P. Wu, et al., "PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems, " Proc. SoCC, pp. 136-139, 2014.
2. M. Bohr, "The new era of scaling in an SoC world, " Proc. ISSCC, pp. 23-28, 2009.
3. K. Arabi, et al., "Power supply noise in SoCs: Metrics, management, measurement, " IEEE D & T, vol. 24(3): 236-244, 2007.
4. J. Chabloz, et al., "Distributed DVFS using rationally-related frequencies and discrete voltage levels, " Proc. ISLPED, pp. 247-252, 2010.
5. V. Tiwari, et al., "Reducing power in high-performance microprocessors, " Proc. DAC, pp. 732-737, 1998.
6. N. Rizvandi, et al., "Multiple frequency selection in DVFS-enabled processors to minimize energy consumption, " John Wiley & Sons, 2012.
7. J. Balcells, et al., "Frequency modulation techniques for EMI reduction in SMPS, " Proc. ECPEA, pp. 8-10, 2005.
8. M. Yadav, et al., "DVFS based on voltage dithering and clock scheduling for GALS systems, " Proc. ASYNC, pp. 118-125, 2012.
9. S. Park, et al., "Accurate modeling of the delay and energy overhead of dynamic voltage and frequency scaling in modern microprocessors, " IEEE TCAD, vol. 32(5), pp. 695-708, 2013.
10. M. Gupta, et al., "Understanding voltage variations in chip multiprocessors using a distributed power-delivery network, " Proc. DATE, pp. 624-629, 2007.
11. W. Lam, et al., "Clock scheduling for power supply noise suppression using genetic algorithm with selective gene therapy, " Proc. ISQED, pp. 327-332, 2003.
12. S. Hall and H. Heck, "Advanced Signal Integrity for High-Speed Digital Designs, " Wiley-IEEE Press, 2009.
13. Y. Kim and L. John, "Automated dI/dt stressmark generation for microprocessor power delivery networks, " Proc. ISLPED, pp. 253-258, 2011.
14. H. Zheng, et al., "On-package decoupling optimization with package macromodels, " Proc. CICC, pp. 723-726, 2003.
15. J. Zhao, et al., "Effects of power/ground via distribution on the power/ground performance of C4/BGA packages, " Proc. EPEP, pp. 177-180, 1998.
16. T. H. Chen, et al., "Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methods, " Proc. DAC, pp. 559-562, 2001.
17. H. Qian, et al., "Power grid analysis using random walks, " IEEE TCAD, vol. 24 (8), pp. 1204-1224, 2005.
18. J. Kozhaya, et al., "A multigrid-like technique for power grid analysis, " IEEE TCAD, vol. 21(10), pp. 1148-1160, 2002.
19. Z. Feng and P. Li, "Multigrid on GPU: Tackling power grid analysis on parallel SIMT platforms, " Proc. ICCAD, pp. 647-654, 2008.
20. X.-D. S. Tan and C.-J. R. Shi, "Fast power/ground network optimization based on equivalent circuit modeling, " Proc. DAC, pp. 550-554, 2001.
21. F. Najm, "Overview of vectorless/early power grid verification, " Proc. ICCAD, pp. 670-677, 2012.
22. P. Evans, et al., "Validation of high-definition electric power delivery network simulation, " Proc. PESG, pp. 1-7, 2010.
23. C. Zhuo, et al., "A cross-layer approach for early-stage power grid design and optimization, " ACM JETC, vol. 12(3):1-25, 2015.
24. V. Pandit, et al., "Power Integrity for I/O Interfaces: With Signal Integrity/Power Integrity Co-Design, " Prentice Hall, 2010.
25. C. Zhuo, et al., "A novel cross-layer framework for early-stage power delivery and architecture co-exploration, " Proc. DAC, pp. 1-6, 2016.
26. E. Khalil, et al., "Learning to branch in mixed integer programming, " Proc. AAAI, pp. 724-731, 2016.