On-package decoupling optimization with package macromodels

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 723-726

  Zheng, Hui ^a   Krauter, Byron ^b   Pileggi, Lawrence ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; MATHEMATICAL MODELS; SIMULATED ANNEALING; SPURIOUS SIGNAL NOISE; SWITCHING CIRCUITS;

CHIP PACKAGE INTERFACE; CLOCK GATING; PACKAGE MACROMODELS; POWER CONSUMPTION; SWITCHING CURRENT;

VLSI CIRCUITS;

EID: 0242695819     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Publishing Company, 1990
2. L. Smith, et al. "Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology," IEEE Transactions on Advanced Packaging, Vol. 22, No. 3, pp. 284-91, August 1999
3. H. Zheng, B. Krauter and L. T. Pileggi, "Electrical Modeling of Integrated-Package Power/Ground Distributions," IEEE Design and Test Magazine, in press.
4. A. Devgan, H. Ji, and W. Dai., "How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K," IEEE/ACM Proc. ICCAD, pp. 150-155, Nov. 2000
5. M. Beattie and L. Pileggi, "Efficient Inductance Extraction via Windowing," IEEE/ACM Proc. 2001 DATE, pp. 430-436, March 2001
6. H. Zheng and L. T. Pileggi, "Robust and Passive Model Order Reduction for Circuit Containing Susceptance Elements," to appear in Proc. IEEE International Conference on Computer Aided Design, Nov. 2002
7. M. Celik, H. Zheng and L. T. Pileggi, "Efficient Reduction of Susceptance-based Package Models Using PRIMA," in Proc. 11th Topical Meeting on Electrical Performance of Electronic Packaging, Oct. 2002