Memory-Aware Genetic Algorithms for Task Mapping on Hard Real-Time Networks-on-Chip

Proceedings - 26th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2018

Volumn , Issue , 2018, Pages 601-608

  Still, Lloid Robert ^a   Indrusiak, Leandro Soares ^a  

^a UNIVERSITY OF YORK   (United Kingdom)

Author keywords

Multi core processing; Real time systems

Indexed keywords

BENCHMARKING; GENETIC ALGORITHMS; INTERACTIVE COMPUTER SYSTEMS; MAPPING; MEMORY ARCHITECTURE; NETWORK-ON-CHIP;

BENCHMARK APPLICATIONS; EXISTING PROBLEMS; HARD REAL-TIME TASK; MEMORY CONSTRAINTS; MULTI-CORE PROCESSING; NETWORKS ON CHIPS; PROBLEM FORMULATION; STATE OF THE ART;

REAL TIME SYSTEMS;

EID: 85048748739     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PDP2018.2018.00101     Document Type: Conference Paper

References (17)

1. A. Agarwal. The Tile Processor: A 64-Core Multicore for Embedded Processing. In 11th Annual Workshop on High Performance Embedded Computing (HPEC), 2007.
2. G. Ascia, V. Catania, M. Palesi. Multi-objective Mapping for Meshbased NoC Architectures. In Proc 2nd Int Conf on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 182-187, 2004.
3. R. Ayari, I. Hafnaoui, G. Beltrame, G. Nicolescu. Schedulabilityguided Exploration of Multi-core Systems. In Int Symposium on Rapid System Prototyping (RSP), 2016.
4. B. D. de Dinechin, Y. Durand, D. van Amstel, A. Ghiti. Guaranteed Services of the NoC of a Manycore Processor. In Proc Int Workshop on Network on Chip Architectures (NoCArc), pages 11-16. ACM, 2014.
5. K. Deb, A. Pratap, S. Agarwal, T. Meyarivan. A fast and elitist multiobjective genetic algorithm: NSGA-II. IEEE Transactions on Evolutionary Computation, 6(2):182-197, 2002.
6. L. S. Indrusiak. End-to-end schedulability tests for multiprocessor embedded systems based on networks-on-chip with priority-preemptive arbitration. Journal of Systems Architecture, 60(7):553-561, 2014.
7. L. S. Indrusiak, A. Burns, B. Nikolic. Analysis of buffering effects on hard real-time priority-preemptive wormhole networks. arXiv:1606.02942, 2016.
8. H. Kashif, S. Gholamian, H. Patel. SLA: A Stage-Level Latency Analysis for Real-Time Communication in a Pipelined Resource Model. IEEE Trans Comput, 64(4):1177-1190, 2015.
9. P. Mesidis and L. S. Indrusiak. Genetic mapping of hard real-time applications onto NoC-based MPSoCsa first approach. In 6th Int Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011.
10. B. Nikolic, H. I. Ali, S. M. Petters, L. M. Pinho. Are Virtual Channels the Bottleneck of Priority-aware Wormhole-switched NoCbased Many-cores In Proc 21st Int Conf on Real-Time Networks and Systems (RTNS), pages 13-22, 2013.
11. M. Palesi, G. Ascia, F. Fazzino, V. Catania. Data encoding schemes in networks on chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(5):774-786, 2011.
12. M Norazizi Sham Mohd Sayuti and Leandro Soares Indrusiak. Real-Time Low-Power Task Mapping in Networks-on-Chip. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 14-19, 2013.
13. Z. Shi and A. Burns. Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching. In IEEE/ACM NOCS Symposium, pages 161-170, 2008.
14. Z. Shi, A. Burns, L. S. Indrusiak. Schedulability Analysis for Real Time On-Chip Communication with Wormhole Switching. International Journal of Embedded and Real-Time Communication Systems (IJERTCS), 1(2), 2010.
15. A. K. Singh, M. Shafique, A. Kumar, J. Henkel. Mapping on multi/many-core systems: Survey of current and emerging trends. In Proc 50th IEEE/ACM Design Automation Conference (DAC), 2013.
16. K. W. Tindell, A. Burns, A. J. Wellings. Allocating hard real-time tasks: An NP-Hard problem made easy. Real-Time Systems, 4(2):145-165, 1992.
17. Q. Xiong, F. Wu, Z. Lu, C. Xie. Extending Real-Time Analysis for Wormhole NoCs. IEEE Trans Comput, 66(9):1532-1546, 2017.