SASSIFI: An architecture-level fault injection tool for GPU application resilience evaluation

ISPASS 2017 - IEEE International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2017, Pages 249-258

  Hari, Siva Kumar Sastry ^a   Tsai, Timothy ^a   Stephenson, Mark ^a   Keckler, Stephen W ^a   Emer, Joel ^a  

^a NVIDIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; ERROR CORRECTION; GRAPHICS PROCESSING UNIT; PROGRAM PROCESSORS; RADIATION HARDENING; SAFETY ENGINEERING;

GENERAL PURPOSE REGISTERS; HIGH PERFORMANCE COMPUTING SYSTEMS; HIGH-ENERGY PARTICLES; INSTRUMENTATION CODE; INSTRUMENTATION TOOLS; MASSIVELY PARALLELS; SAFETY-CRITICAL EMBEDDED SYSTEMS; TOOLS AND TECHNIQUES;

ERRORS;

EID: 85027443168     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2017.7975296     Document Type: Conference Paper

References (30)

1. M. Stephenson, S. K. S. Hari, Y. Lee, E. Ebrahimi, D. R. Johnson, D. Nellans, M. O'Connor, and S. W. Keckler, "Flexible Software Profiling of GPU Architectures, " in Proceedings of the International Symposium on Computer Architecture (ISCA), 2015.
2. NVIDIA, "CUPTI :: CUDA Toolkit Documentation, " http://docs.nvidia.com/cuda/cupti/index.html, 2014.
3. Exascale Co-Design Center for Materials in Extreme Environments (ExMatEX), "CoMD: Classical Molecular Dynamics Proxy Application, " http://exmatex.github.io/CoMD.
4. Lawrence Livermore National Laboratory, "Livermore Unstructured Lagrangian Explicit Shock Hydrodynamics (LULESH) 2.0, " http://codesign.llnl.gov/lulesh.php, 2013.
5. S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S.-H. Lee, and K. Skadron, "Rodinia: A Benchmark Suite for Heterogeneous Computing, " in Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), 2009.
6. S. K. S. Hari, S. V. Adve, H. Naeimi, and P. Ramachandran, "Relyzer: Exploiting Application-level Fault Equivalence to Analyze Application Resiliency to Transient Faults, " in Proceedings of the International Conference on Architectural Support for Programming Languages and Operation Systems (ASPLOS), 2012.
7. B. Fang, K. Pattabiraman, M. Ripeanu, and S. Gurumurthi, "GPUQin: A Methodology for Evaluating the Error Resilience of GPGPU Applications, " in Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), 2014.
8. G. Li, K. Pattabiraman, C.-Y. Cher, and P. Bose, "Understanding Error Propagation in GPGPU Applications, " in Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis (SC), 2016.
9. J. Wei, A. Thomas, G. Li, and K. Pattabiraman, "Quantifying the Accuracy of High-Level Fault Injection Techniques for Hardware Faults, " in Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2014.
10. NVIDIA, "Profiler Users's Guide, " http://docs.nvidia.com/cuda/profiler-users-guide, September 2015.
11. NVIDIA, "NVIDIA's Next Generation CUDA Compute Architecture: Kepler GK110, " https://www.nvidia.com/content/PDF/kepler/NVIDIA-Kepler-GK110-Architecture-Whitepaper.pdf, 2012.
12. NVIDIA, "NVIDIA GeForce GTX 980 Featuring Maxwell, The Most Advanced GPU Ever Made." http://international.download.nvidia.com/geforce-com/international/pdfs/GeForceGTX980WhitepaperFINAL.PDF, 2014.
13. J. Wadden, A. Lyashevsky, S. Gurumurthi, V. Sridharan, and K. Skadron, "Real-World Design and Evaluation of Compiler- Managed GPU Redundant Multithreading, " in Proceedings of the International Symposium on Computer Architecture (ISCA), 2014.
14. S. Lee and W. W. Ro, "Parallel GPU Architecture Simulation Framework Exploiting Work Allocation Unit Parallelism, " in Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), 2013.
15. C. Celio, D. A. Patterson, and K. Asanovic, "The Berkeley Outof- Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor, " in Technical Report No. UCB/EECS-2015-167, 2015.
16. NVIDIA, "CUDA-GDB :: CUDA Toolkit Documentation, " http://docs.nvidia.com/cuda/cuda-gdb/index.html, 2014.
17. NVIDIA, "PTX ISA :CUDA Toolkit Documentation, " http://docs.nvidia.com/cuda/parallel-Thread-execution/September 2015.
18. S. Li, V. Sridharan, S. Gurumurthi, and S. Yalamanchili, "Softwarebased Dynamic Reliability Management for GPU Applications, " in International Reliability Physics Symposium, 2016.
19. S. Tselonis and D. Gizopoulos, "GUFI: A Framework for GPUs Reliability Assessment, " in Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), 2016.
20. V. Sridharan and D. Kaeli, "Eliminating Microarchitectural Dependency from Architectural Vulnerability, " in Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA), 2009.
21. S. S. Mukherjee, C. Weaver, J. Emer, S. K. Reinhardt, and T. Austin, "A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor, " in Proceedings of the International Symposium on Microarchitecture (MICRO), December 2003.
22. A. Biswas, P. Racunas, R. Cheveresan, J. Emer, S. S. Mukherjee, and R. Rangan, "Computing Architectural Vulnerability Factors for Address-Based Structures, " in Proceedings of the International Symposium on Computer Architecture (ISCA), 2005.
23. J. Tan, N. Goswami, T. Li, and X. Fu, "Analyzing Soft-error Vulnerability on GPGPU Microarchitecture, " in Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), 2011.
24. H. Jeon, M. Wilkening, V. Sridharan, S. Gurumurthi, and G. H. Loh, "Architectural Vulnerability Modeling and Analysis of Integrated Graphics Processors, " in Workshop on Silicon Errors in Logic - System Effects (SELSE), 2013.
25. N. Farazmand, R. Ubal, and D. Kaeli, "Statistical Fault Injection- Based AVF Analysis of a GPU Architecure, " in Workshop on Silicon Errors in Logic - System Effects (SELSE), 2012.
26. G. P. Saggese, N. J. Wang, Z. T. Kalbarczyk, S. J. Patel, and R. K. Iyer, "An Experimental Study of Soft Errors in Microprocessors, " IEEE Micro, vol. 25, no. 6, pp. 30-39, 2005.
27. M. Maniatakos, N. Karimi, C. Tirumurti, A. Jas, and Y. Makris, "Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller, " IEEE Transactions on Computers, vol. 60, no. 9, pp. 1260-1273, 2011.
28. H. Cho, S. Mirkhani, C.-Y. Cher, J. A. Abraham, and S. Mitra, "Quantitative Evaluation of Soft Error Injection Techniques for Robust System Design, " in Design Automation Conference (DAC), 2013.
29. E. Cheng, S. Mirkhani, L. G. Szafaryn, C. Y. Cher, H. Cho, K. Skadron, M. Stan, K. Lilja, J. Abraham, P. Bose, and S. Mitra, "CLEAR: Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores, " in Design Automation Conference (DAC), 2016.
30. M. Gschwind, V. Salapura, C. Trammell, and S. A. McKee, "Soft- Beam: Precise Tracking of Transient Faults and Vulnerability Analysis at Processor Design Time, " in Proceedings of the International Conference on Computer Design (ICCD), 2011.