Efficient modeling of memoryarrays in symbolic simulation

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1254, Issue , 1997, Pages 388-399

  Velev, Miroslav ^a   Bryant, Randal E ^b   Jain, Alok ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b Carnegie Mellon University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; EMBEDDED SYSTEMS; FORMAL VERIFICATION; MEMORY ARCHITECTURE; MODEL CHECKING;

BEHAVIORAL MODEL; BOOLEAN EXPRESSIONS; DATA EXPRESSION; MEMORY LOCATIONS; SOFTWARE INTERFACES; SYMBOLIC SIMULATION; SYMBOLIC TRAJECTORY EVALUATION; TRANSISTOR LEVEL;

COMPUTER SOFTWARE;

EID: 84947438436     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-63166-6_38     Document Type: Conference Paper

References (8)

1. D.L. Beatty, R. E. Bryant, and C.-J. H. Seger, "Synchronous Circuit Verification by Symbolic Simulation: An Illustration," Sixth MIT Conference on Advanced Research in VLSI, 1990, pp. 98-112.
2. R.E. Bryant, D. E. Beatty, and C.-J. H. Seger, "Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation," 28th Design Automation Conference, June, 1991, pp. 297-402.
3. J.R. Butch, E. M. Clarke, K. L. McMillan, and D. L. Dill, "Sequential Circuit Verification Using Symbolic Model Checking," 27th Design Automation Conference, June, 1990, pp. 46-51.
4. J.R. Butch, E. M. Clarke, and D. E. Long, "Representing Circuits More Efficiently in Symbolic Model Checking," 28th Design Automation Conference, June, 1991, pp. 403-407.
5. J.R. Butch, and D. L. Dill, "Automated Verification of Pipelined Microprocessor Control," CAV '94, D. L. Dill, ed., LNCS 818, Springer-Verlag, June, 1994, pp. 68-80.
6. E.M. Clarke, O. Grnmberg, and D. E. Long, "Model Checking and Abstracfion," 19th Annual ACM Symposium on Principles of Programming Languages, 1992, pp. 343-354.
7. M. Pandey, and R. E. Bryant, "Exploiting Symmetry When Verifying Transistor-Level Circuits by Symbolic Trajectory Evaluation," CAV '97, June, 1997.
8. C.-J. H. Seger, and R. E. Bryant, "Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories," Formal Methods in System Design, Vol. 6, No. 2 (March, 1995), pp. 147-190.