Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1254, Issue , 1997, Pages 244-255

  Pandey, Manish ^a   Bryant, Randal E ^a  

^a Carnegie Mellon University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; DATA HANDLING; STATIC RANDOM ACCESS STORAGE; TIMING CIRCUITS;

CIRCUIT STRUCTURES; GRAPH ISOMORPHISM; ORDERS OF MAGNITUDE; STATIC RANDOM ACCESS MEMORY; STRUCTURAL SYMMETRY; SYMBOLIC SIMULATION; SYMBOLIC TRAJECTORY EVALUATION; TRANSISTOR LEVEL;

MODEL CHECKING;

EID: 84863929714     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-63166-6_25     Document Type: Conference Paper

References (10)

1. S. Aggarwal, R. P. Kurshan, and K. Sabnani. A calculus for protocol specification and validation. In Protocol Specification, Testing and Verification, volume 3, 1983.
2. Derek L. Beatty and Randal E. Bryant. Fast incremental circuit analysis using extracted hierarchy. In 25th A CM/IEEE Design Automation Conference, pages 495-500, June 1988.
3. Randal E. Bryant. Boolean analysis of MOS circuits. IEEE Transactions on Computer-Aided Design, CAD-6(4):634-649, July 1987.
4. Randal E. Bryant. Formal verification of memory circuits by switch-level simulation. IEEE Transactions on Computer-Aided Design, CAD-10(1):94-102, January 1991.
5. Randal E. Bryant and Carl-Johan H. Seger. Formal verification of digital circuits using symbolic ternary system models. In Robert P. Kurshan, editor, Computer Aided Verification, pages 121-146, 1990.
6. Edmund M. Clarke, Robert Enders, Thomas Filkorn, and Somesh Jha. Exploiting symmetry in temporal logic model checking. Formal Methods in System Design, 9:77-104, 1996.
7. E. Allen Emerson and A. Prasad Sistla. Symmetry and model checking. Formal Methods in System Design, 9:105-131, 1996.
8. C. Norris Ip and David L. Dill. Better verification through symmetry. Formal Methods in System Design, 9:41-75, 1996.
9. Manish Pandey, Richard Raimi, Derek L. Beatty, and Randal E. Bryant. Formal verification of PowerPC(TM) arrays using symbolic trajectory evaluation. In 33rd A CM/IEEE Design Automation Conference, pages 649-654, June 1996.
10. Carl-Johan H. Seger and Randal E. Bryant. Formal verification by symbolic evaluation of partially-ordered trajectories. Formal Methods in System Design, 6:147-189, 1995.