Effective Work Function Engineering of TaxCyMetal Gate on Hf-based Dielectrics

IEEE Electron Device Letters

Volumn 28, Issue 3, 2007, Pages 201-203

  Yen, F Y ^a   Hung, C L ^a   Hou, Y T ^a   Hsu, P F ^a   Chang, V S ^a   Lim, P S ^a   Yao, L G ^a   Jiang, J C ^a   Lin, H J ^a   Chen, C C ^a   Jin, Y ^a   Jang, S M ^a   Tao, H J ^a   Cher, S C ^a   Liang, M S ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Effective work function (EWF); HfO2; HfSiON; metal gate; plasma nitridation (PN); tantalum carbide (TaC); thermal nitridation (TN)

Indexed keywords

EID: 85008040399     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/LED.2007.891271     Document Type: Article

References (12)

1. G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-k gate dielectrics: Current status and materials properties considerations,” J. Appl. Phys., vol. 89, no. 10, pp. 5243–5275, May 2001.
2. M. L. Green, E. P. Gusev, R. Degraeve, and E. Garfunkel, “Ultrathin (< 4 nm) Si02 and Si-O-N gate dielectrics layers for silicon microelectronics: Understanding the processing, structure and physical and electrical limits,” J. Appl. Phys. Rev., vol. 90, no. 5, pp. 2057–2121, Jan. 2001.
3. G. Pourtois, A. Lauwers, J. Kittl, L. Pantisano, B. Sorée, S. De Gendt, W. Magnus, M. Heyns, and K. Maex, “First-principle calculations on gate/dielectric interfaces: On the origin of work function shifts,” Microelectron. Eng., vol. 80, no. 1, pp. 272–279, Jun. 2005.
4. I. De, D. Johri, A. Srivastava, and C. M. Osburn, “Impact of gate workfunction on device performance at the 50 nm technology node,” Solid-State Electron., vol. 44, no. 6, pp. 1077–1080, Jun. 2000.
5. H. Y. Yu, C. Ren, Y. C. Yeo, J. F. Kang, X. P. Wang, H. H. H. Ma, M. F. Li, D. S. H. Chan, and D. L. Kwong, “Fermi pinning-induced thermal instability of metal-gate work function,” IEEE Electron Device Lett., vol. 25, no. 5, pp. 337–339, May 2004.
6. Y. T. Hou, F. Y. Yen, P. F. Hsu, V. S. Chang, P. S. Lim, C. L. Hung, L. G. Yao, J. C. Jiang, H. J. Lin, Y. Jin, S. M. Jang, H. J. Tao, S. C. Chen, and M. S. Liang, “High performance tantalum carbide metal gate stacks for nMOSFET application,” in IEDM Tech. Dig., 2005, pp. 72–75.
7. J. K. Schaeffer, C. Capasso, L. R. C. Fonseca, S. Samavedam, D. C. Gilmer, Y. Liang, S. Kalpat, B. Adetutu, H.-H. Tseng, Y. Shiho, A. Demkov, R. Hegde, W. J. Taylor, R. Gregory, J. Jiang, E. Luckowski, M. V. Raymond, K. Moore, D. Triyoso, D. Roan, B. E. White, Jr., and P. J. Tobin, “Challenges for the integration of metal gate electrodes,” in IEDM Tech. Dig., 2004, pp. 287–290.
8. H. H. Tseng, C. C. Capasso, J. K. Schaeffer, E. A. Hebert, P. J. Tobin, D. C. Gilmer, D. Triyoso, M. E. Ramón, S. Kalpat, E. Luckowski, W. J. Taylor, Y. Jeon, O. Adetutu, R. I. Hegde, R. Noble, M. Jahanbani, C. El Chemali, and B. E. White, “Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/Hf02 stack,” in IEDM Tech. Dig., 2004, pp. 821–824.
9. H. C. Wen, H. N. Alshareef, H. Luan, K. Choi, P. Lysaght, H. R. Harris, C. Huffman, G. A. Brown, G. Bersuker, P. Zeitzoff, H. Huff, P. Majhi, and B. H. Lee, “Systematic investigation of amorphous transition-metal-silicon-nitride electrodes for metal gate CMOS applications,” in VLSI Tech. Dig., 2005, pp. 46–47.
10. R. Jha, J. Gurganos, Y. H. Kim, R. Choi, J. Lee, and V. Misra, “A capacitance-based methodology for work function extraction of metals on high-k,” IEEE Electron Device Lett., vol. 25, no. 6, pp. 420–423, Jun. 2004.
11. Y. C. Yeo, P. Ranade, T. J. King, and C. Hu, “Effects of high-k gate dielectric materials on metal and silicon gate workfunctions,” IEEE Electron Device Lett., vol. 23, no. 6, pp. 342–344, Jun. 2002.
12. M. S. Joo, B. J. Cho, N. Balasubramanian, and D. L. Kwong, “Thermal instability of effective work function in metal/high-k stack and its material dependence,” IEEE Electron Device Lett., vol. 25, no. 11, pp. 716–718, Nov. 2004.