Design and Implementation of the POWER6 Microprocessor

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 1, 2008, Pages 21-28

  Stolt, Benjamin ^a   Mittlefehldt, Yonatan ^a   Dubey, Sanjay ^a   Mittal, Gaurav ^a   Lee, Mike ^a   Friedrich, Joshua ^a   Fluhr, Eric ^a  

^a IBM   (United States)

Author keywords

65 nm SOI process; ABIST; array; circuit design methodology; clocking; custom circuits; dual core; latch; LBIST; microprocessor; power; POWER6; register file; RLM methodology; SRAM; timing

Indexed keywords

EID: 85008036617     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.2007.910963     Document Type: Article

References (7)

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