Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 07-10-November-2016, Issue , 2016, Pages

  Wang, Ying ^a   Li, Huawei ^a   Li, Xiaowei ^a  

^a INSTITUTE OF COMPUTING TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; BUDGET CONTROL; COMPUTER AIDED DESIGN; DATA COMPRESSION; DIGITAL STORAGE; EMBEDDED SYSTEMS; ENERGY UTILIZATION; LEARNING SYSTEMS; NEURAL NETWORKS; REDUNDANCY; ROBOTICS; SPEECH RECOGNITION;

BUILT-IN REDUNDANCY; COMPRESSION METHODS; COMPUTE RESOURCES; CONVOLUTIONAL NEURAL NETWORK; DATA REDUNDANCY; DETECTION MECHANISM; ITS APPLICATIONS; NOVEL APPLICATIONS;

MEMORY ARCHITECTURE;

EID: 85001086148     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2966986.2967068     Document Type: Conference Paper

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