Going deeper with embedded FPGA platform for convolutional neural network

FPGA 2016 - Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Volumn , Issue , 2016, Pages 26-35

  Qiu, Jiantao ^a   Wang, Jie ^a   Yao, Song ^a   Guo, Kaiyuan ^a   Li, Boxun ^a   Zhou, Erjin ^a   Yu, Jincheng ^a   Tang, Tianqi ^a   Xu, Ningyi ^b   Song, Sen ^a,c   Wang, Yu ^a   Yang, Huazhong ^a  

^a TSINGHUA UNIVERSITY   (China)

^b MICROSOFT RESEARCH ASIA   (China)

^c NONE   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER VISION; CONVOLUTION; EMBEDDED SYSTEMS; LOGIC GATES; NEURAL NETWORKS; RECONFIGURABLE HARDWARE; SMARTPHONES;

ACCELERATOR DESIGN; CONVOLUTIONAL NEURAL NETWORK; DATA QUANTIZATIONS; FPGA ACCELERATORS; IN-DEPTH ANALYSIS; LIMITED BANDWIDTH; RESOURCE UTILIZATIONS; WORKING FREQUENCY;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84966533810     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2847263.2847265     Document Type: Conference Paper

References (30)

1. O. Russakovsky, J. Deng, H. Su, J. Krause, S. Satheesh, S. Ma, Z. Huang, A. Karpathy, A. Khosla, M. Bernstein, A. C. Berg, and L. Fei-Fei, "ImageNet Large Scale Visual Recognition Challenge," pp. 211-252, 2015.
2. A. Krizhevsky, I. Sutskever, and G. E. Hinton, "Imagenet classification with deep convolutional neural networks," in NIPS, 2012, pp. 1097-1105.
3. M. D. Zeiler and R. Fergus, "Visualizing and understanding convolutional networks," in ECCV, 2014, pp. 818-833.
4. C. Szegedy, W. Liu, Y. Jia, P. Sermanet, S. Reed, D. Anguelov, D. Erhan, V. Vanhoucke, and A. Rabinovich, "Going deeper with convolutions," arXiv preprint arXiv:1409.4842, 2014.
5. K. He, X. Zhang, S. Ren, and J. Sun, "Deep residual learning for image recognition," arXiv preprint arXiv:1512.03385, 2015.
6. C. Zhang, P. Li, G. Sun, Y. Guan, B. Xiao, and J. Cong, "Optimizing FPGA-based accelerator design for deep convolutional neural networks," in Proceedings of ISFPGA. ACM, 2015, pp. 161-170.
7. T. Chen, Z. Du, N. Sun, J. Wang, C. Wu, Y. Chen, and O. Temam, "Diannao: A small-footprint high-throughput accelerator for ubiquitous machine-learning," in ASPLOS, vol. 49, no. 4. ACM, 2014, pp. 269-284.
8. Y. Chen, T. Luo, S. Liu, S. Zhang, L. He, J. Wang, L. Li, T. Chen, Z. Xu, N. Sun et al., "Dadiannao: A machine-learning supercomputer," in MICRO. IEEE, 2014, pp. 609-622.
9. D. Liu, T. Chen, S. Liu, J. Zhou, S. Zhou, O. Teman, X. Feng, X. Zhou, and Y. Chen, "Pudiannao: A polyvalent machine learning accelerator," in ASPLOS. ACM, 2015, pp. 369-381.
10. Z. Du, R. Fasthuber, T. Chen, P. Ienne, L. Li, T. Luo, X. Feng, Y. Chen, and O. Temam, "Shidiannao: Shifting vision processing closer to the sensor," in ISCA. ACM, 2015, pp. 92-104.
11. S. Chakradhar, M. Sankaradas, V. Jakkula, and S. Cadambi, "A dynamically configurable coprocessor for convolutional neural networks," in ISCA, vol. 38, no. 3. ACM, 2010, pp. 247-257.
12. C. Farabet, B. Martini, B. Corda, P. Akselrod, E. Culurciello, and Y. LeCun, "Neuflow: A runtime reconfigurable dataflow processor for vision," in CVPRW. IEEE, 2011, pp. 109-116.
13. C. Farabet, C. Poulet, J. Y. Han, and Y. LeCun, "Cnp: An FPGA-based processor for convolutional networks," in FPL. IEEE, 2009, pp. 32-37.
14. Y. LeCun, L. Bottou, Y. Bengio, and P. Haffner, "Gradient-based learning applied to document recognition," Proceedings of the IEEE, vol. 86, no. 11, pp. 2278-2324, 1998.
15. A. S. Razavian, H. Azizpour, J. Sullivan, and S. Carlsson, "Cnn features off-The-shelf: An astounding baseline for recognition," in CVPRW. IEEE, 2014, pp. 512-519.
16. K. Simonyan and A. Zisserman, "Very deep convolutional networks for large-scale image recognition," arXiv preprint arXiv:1409.1556, 2014.
17. S. J. Hanson and L. Y. Pratt, "Comparing biases for minimal network construction with back-propagation," in NIPS, 1989, pp. 177-185.
18. Y. LeCun, J. S. Denker, S. A. Solla, R. E. Howard, and L. D. Jackel, "Optimal brain damage," in NIPS, vol. 89, 1989.
19. B. Hassibi and D. G. Stork, Second order derivatives for network pruning: Optimal brain surgeon. Morgan Kaufmann, 1993.
20. S. Han, J. Pool, J. Tran, and W. J. Dally, "Learning both weights and connections for efficient neural networks," arXiv preprint arXiv:1506.02626, 2015.
21. G. H. Golub and C. F. Van Loan, "Matrix computations. 1996," Johns Hopkins University, Press, Baltimore, MD, USA, pp. 374-426, 1996.
22. E. L. Denton, W. Zaremba, J. Bruna, Y. LeCun, and R. Fergus, "Exploiting linear structure within convolutional networks for efficient evaluation," in NIPS, 2014, pp. 1269-1277.
23. X. Zhang, J. Zou, X. Ming, K. He, and J. Sun, "Efficient and accurate approximations of nonlinear convolutional networks," arXiv preprint arXiv:1411.4229, 2014.
24. M. Jaderberg, A. Vedaldi, and A. Zisserman, "Speeding up convolutional neural networks with low rank expansions," arXiv preprint arXiv:1405.3866, 2014.
25. C. Farabet, Y. LeCun, K. Kavukcuoglu, E. Culurciello, B. Martini, P. Akselrod, and S. Talay, "Large-scale FPGA-based convolutional networks," Machine Learning on Very Large Data Sets, vol. 1, 2011.
26. M. Sankaradas, V. Jakkula, S. Cadambi, S. Chakradhar, I. Durdanovic, E. Cosatto, and H. Graf, "A massively parallel coprocessor for convolutional neural networks," in ASAP, July 2009, pp. 53-60.
27. D. Larkin, A. Kinane, and N. O'Connor, "Towards hardware acceleration of neuroevolution for multimedia processing applications on mobile devices," in Neural Information Processing. Springer, 2006, pp. 1178-1188.
28. Y. Jia, E. Shelhamer, J. Donahue, S. Karayev, J. Long, R. Girshick, S. Guadarrama, and T. Darrell, "Caffe: Convolutional architecture for fast feature embedding," arXiv preprint arXiv:1408.5093, 2014.
29. B. Bosi, G. Bois, and Y. Savaria, "Reconfigurable pipelined 2-d convolvers for fast digital signal processing," VLSI, vol. 7, no. 3, pp. 299-308, 1999.
30. V. Gokhale, J. Jin, A. Dundar, B. Martini, and E. Culurciello, "A 240 g-ops/s mobile coprocessor for deep neural networks," in CVPRW. IEEE, 2014, pp. 696-701.