Optimizing FPGA-based accelerator design for deep convolutional neural networks

FPGA 2015 - 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Volumn , Issue , 2015, Pages 161-170

  Zhang, Chen ^a   Li, Peng ^b   Sun, Guangyu ^a,c   Guan, Yijin ^a   Xiao, Bingjun ^b   Cong, Jason ^a,b,c  

^a PEKING UNIVERSITY   (China)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UCLA Joint Research Institute in Science and Engineering   (United States)

Author keywords

Acceleration; Convolutional neural network; FPGA; Rooine model

Indexed keywords

ACCELERATION; BANDWIDTH; CACHE MEMORY; COMPLEX NETWORKS; CONVOLUTION; DESIGN; EYE PROTECTION; IMAGE MATCHING; IMAGE RECOGNITION; INTEGRATED CIRCUIT DESIGN; LEARNING ALGORITHMS; LOGIC GATES; NEURAL NETWORKS; RECONFIGURABLE HARDWARE;

ACCELERATOR DESIGN; ANALYTICAL DESIGN; CONVOLUTIONAL NEURAL NETWORK; CRITICAL PROBLEMS; GENERIC PROCESSORS; MODERN APPLICATIONS; OPTIMIZATION TECHNIQUES; RESOURCE REQUIREMENTS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84962921765     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2684746.2689060     Document Type: Conference Paper

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