High-speed architecture for a programmable frequency divider and a dual-modulus prescaler

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 5, 1996, Pages 744-748

  Larsson, Patrik ^a,b  

^a LINKÖPING UNIVERSITY   (Sweden)

^b LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DETECTORS; FLIP FLOP CIRCUITS; FREQUENCY DIVIDING CIRCUITS; LOGIC CIRCUITS; SHIFT REGISTERS; TRANSISTORS;

DUAL MODULAR PRESCALER; HIGH SPEED ARCHITECTURE; MAXIMUM CLOCK FREQUENCY; PROGRAMMABLE FREQUENCY DIVIDER;

CMOS INTEGRATED CIRCUITS;

EID: 0030145220     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.509859     Document Type: Article

References (12)

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