A 1.2 GHz CMOS dual-modulus prescaler using new dynamic d-type flip-flops

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 5, 1996, Pages 749-752

  Chang, Byungsoo ^a   Park, Joonbae ^a   Kim, Wonchan ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LOGIC GATES; MOS DEVICES; SEQUENTIAL CIRCUITS; TRANSISTORS;

ASYNCHRONOUS COUNTER; FRACTIONAL DIVISION RATIO; MAXIMUM OPERATING FREQUENCY; SYNCHRONOUS COUNTER;

CMOS INTEGRATED CIRCUITS;

EID: 0030143673     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.509860     Document Type: Article

References (7)

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2. H. P. Singh, R. A. Sadler, W. J. Tanis, and A. N. Schenberg, "GaAs prescalers and counters for Fast-settling frequency synthesizers," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 239-245, 1990.
3. H.-I Cong, J. M. Andrews, D. M. Boulin, S.-C. Fang, S. J. Hillenius, and J. A. Michejda, "A 2-GHz CMOS dual-modulus prescaler IC," in ISSCC Dig. Tech. Papers, Feb. 1988, pp. 138-139.
4. R. Rogenmoser, Q. Huang, and F. Piazza, "1.57 GHz asynchronous ans 1.4 GHz dual-modulus 1.2 μm CMOS prescalers," in Proc. CICC, May 1994, pp. 16.3.1-16.3.4.
5. B. Razavi, K. F. Lee, and R.-H. Yan, "A 13.4-GHz CMOS frequency divider," in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 176-177.
6. J. Yuan and C. Svensson, "High-speed CMOS circuit technique," IEEE7. Solid-State Circuits, vol. 24, no. 2, pp. 62-70, 1989.
7. N. Foroudi and T. A. Kwasniewski, "CMOS high-speed dual-modulus frequency divider for RF frequency synthesis," IEEE J. SolidState Circuits, vol. 30, no. 2, pp. 93-100, 1995.