Bit-serial test pattern generation by an accumulator behaving as a non-linear feedback shift register

Proceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002

Volumn , Issue , 2002, Pages 152-157

  Dimitrakopoulos, G ^a   Nikolos, D ^a,b   Bakalis, D ^a,b  

^a UNIVERSITY OF PATRAS   (Greece)

^b University of Patras and Computer Technology Institute   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; NUMBER THEORY; RECONFIGURABLE HARDWARE; SHIFT REGISTERS;

ARITHMETIC FUNCTIONS; BIT-SERIAL; NON LINEAR; RANDOM PROPERTIES; SOFTWARE IMPLEMENTATION; TEST PATTERN; TEST RESPONSE;

SOFTWARE TESTING;

EID: 84962633557     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2002.1030199     Document Type: Conference Paper

References (17)

1. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, NY, 1990.
2. P. H. Bardell, W. H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudo-Random Techniques, NY: Wiley, 1987.
3. M. Bushnell and V. Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed Signal VLSI circuits, Kluwer Academic Publishers, 2000.
4. H. J. Wunderlich, BIST for systems-on-a-chip, Integration, The VLSI Journal, vol. 26, no.1-2, pp. 55-78, Dec. 1998.
5. J.Rajski and J.Tyszer, Arithmetic Built-In Self-Test for Embedded Systems, Prentice Hall, 1998.
6. Rajski J., Tyszer J., Test Response Compaction in Accumulators with Rotate Carry Adders, IEEE Trans. on CAD, vol. 12, no.4, pp. 531-539, April 1993.
7. Stroele A. P., Test Response Compaction Using Arithmetic Functions, Proc. of IEEE VTS, pp. 380-386, 1996.
8. Gupta S., Rajski J. and Tyszer J., Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns, IEEE Trans. on Comp., vol. 45, no. 8, pp. 939-949, Aug. 1996.
9. Stroele A. P., BIST Pattern Generators Using Addition and Subtraction Operations, JETTA, vol. 11, pp. 69-80, Aug. 1997.
10. J.Rajski and J.Tyszer, Multiplicative Window Generators of Pseudo-random Test Vectors, Proc. of European Design and Test Conference, pp. 42-48, 1996.
11. th IEEE VLSI Test Symposium, pp 78-84, 1998.
12. D. Bakalis, D. Nikolos and X. Kavousianos, Test Response Compaction by an Accumulator behaving as a Multiple Input Non-Linear Feedback Shift Register. Proc. of IEEE ITC, pp. 804-811, 2000.
13. nd IEEE ISQED, pp. 350-355, 2001.
14. D.E.Knuth, The Art of Computer Programming, Vol. 2, Addison-Wesley, 1981.
15. R. Gold, Optimal Binary Sequences for Spread Spectrum Multiplexing, IEEE Trans. on Information Theory, vol. IT-B, pp. 619-621, October 1967.
16. F. Brglez and H. Fujiwara, A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN, Proc. of IEEE ISCAS, 1985.
17. F. Brglez, D.Bryan and K.Kozminski, Combinational Profiles of Sequential Benchmark Circuits, Proc. of IEEE ISCAS, pp. 1929-1934, 1989.