Bit serial pattern generation and response compaction using arithmetic functions

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1998, Pages 78-84

  Stroele, A P ^a  

^a UNIVERSITY OF KARLSRUHE   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; DATA COMPRESSION; ELECTRIC FAULT LOCATION; FLOWCHARTING; LOGIC CIRCUITS; PATTERN RECOGNITION;

TEST RESPONSE;

INTEGRATED CIRCUIT TESTING;

EID: 0032318588     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)