On accumulator-based bit-serial test response compaction schemes

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2001-January, Issue , 2001, Pages 350-355

  Bakalis, D ^a   Nikolos, D ^a   Vergos, H T ^a   Kavousianos, X ^a  

^a UNIVERSITY OF PATRAS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; LOGIC CIRCUITS; SHIFT REGISTERS;

ARITHMETIC CIRCUIT; BENCHMARK CIRCUIT; DATA PATHS; FAULT COVERAGES; PARALLEL TEST; RESPONSE COMPACTION; SPECIAL PURPOSE PROCESSORS; TESTING STRUCTURES;

COMPACTION;

EID: 10444279378     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2001.915255     Document Type: Conference Paper

References (9)

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