BooSTER: Speeding up RTL property checking of digital designs by word-level abstraction

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2102, Issue , 2001, Pages 373-377

  Johannsen, Peer ^a  

^a SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTING; COMPUTER AIDED ANALYSIS; MODEL CHECKING;

DESIGN SIZE; DIGITAL DESIGNS; POST-PROCESSOR; PROPERTY CHECKING; REDUCED MODEL; SCALE DOWN; SCALED-DOWN VERSIONS; WORD LEVEL;

DESIGN;

EID: 84958777591     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44585-4_35     Document Type: Conference Paper

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