An efficient hierarchical timing-driven Steiner tree algorithm for global routing

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 473-478

  Xu, Jingyu ^a   Hong, Xianlong ^a   Jing, Tong ^a   Cai, Yici ^a   Gu, Jun ^b  

^a TSINGHUA UNIVERSITY   (China)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; DESIGN; DYNAMIC PROGRAMMING; HEURISTIC METHODS; HEURISTIC PROGRAMMING; INTEGRATED CIRCUIT TESTING; MULTIPROCESSING SYSTEMS;

CRITICAL PATHS; DYNAMIC PROGRAMMING TECHNIQUES; EFFICIENT STRATEGY; GLOBAL ROUTING; HEURISTIC APPROACH; SOURCE TO SINKS; STEINER TREE PROBLEM; TREE CONSTRUCTION;

TREES (MATHEMATICS);

EID: 84962229213     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994965     Document Type: Conference Paper

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